From patchwork Fri Jun 12 19:10:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 483734 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id E34F6140497 for ; Sat, 13 Jun 2015 05:15:04 +1000 (AEST) Received: from localhost ([::1]:53481 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3UPu-0006fY-QF for incoming@patchwork.ozlabs.org; Fri, 12 Jun 2015 15:15:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48261) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3ULk-0007Wn-Rf for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z3ULf-0003GM-Vp for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:44 -0400 Received: from mail-qg0-f44.google.com ([209.85.192.44]:35920) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z3ULf-0003GG-T5 for qemu-devel@nongnu.org; Fri, 12 Jun 2015 15:10:39 -0400 Received: by qgep100 with SMTP id p100so14295831qge.3 for ; Fri, 12 Jun 2015 12:10:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=o1fuxdZ40SMnEtC0TrVP4l0lKAMc9P11MmeNKTjuF1s=; b=VoUs9/LMsazNBjelhRtxxRfbV4CVRd7Z0KuV6n3YuAaqB9UevE7E/9QV1Zjjs8eTqA uVQh0eT6/jXm5EIIYFqKZc8GMnH17rjjz/p+Ljw5E3679574oZK/vT7oQFzIFlXHMj/y bYFWYd3G/Ew2d+ijVGnjWAyNq6chh0452C3ehJ+Q3Xbr91RgyZS3yvdctfWDDWManQgF MbgN3qyzbKc0WxUv9QDili4kQd8/BG2ywG/sI3WF+32E0exlK+qEfaVIq075XTrcVw9x WPK8/vyUyn3qHfqDDo9wCztgmWY/XLhzp3KUWUVlvUqa9Ne+mI9SzI3Y9hVOEmHAh6eT aO/w== X-Gm-Message-State: ALoCoQkumn47IxZoBV6ViXaYYxL9gGLOcu8welsOeBu8r8/aU1cWNl3Wz2k1aZlRFI16zhySgxyd X-Received: by 10.55.40.66 with SMTP id o63mr33941918qkh.47.1434136239668; Fri, 12 Jun 2015 12:10:39 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id r12sm1259379qkr.2.2015.06.12.12.10.39 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 12 Jun 2015 12:10:39 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Fri, 12 Jun 2015 12:10:38 -0700 Message-Id: <632918cc48786e868ea18aa6bd12f70597994cad.1434066412.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.3.3.g905f831 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.44 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, alistair.francis@xilinx.com, zach.pfeffer@xilinx.com, jues@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v2 06/13] arm: Add has-mpu property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org For processors that support MPUs, add a property to de-feature it. This is similar to the implementation of the EL3 feature. The processor definition in init sets ARM_FEATURE_MPU if it can support an MPU. post_init exposes the property, defaulting to true. If cleared by the instantiator, ARM_FEATURE_MPU is then removed at realize time. This is to support R profile processors that may or may-not have an MPU configured. Signed-off-by: Peter Crosthwaite --- target-arm/cpu-qom.h | 3 +++ target-arm/cpu.c | 13 +++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 19c8e9c..30832d9 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -103,6 +103,9 @@ typedef struct ARMCPU { /* CPU has security extension */ bool has_el3; + /* CPU has memory protection unit */ + bool has_mpu; + /* PSCI conduit used to invoke PSCI methods * 0 - disabled, 1 - smc, 2 - hvc */ diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..82ac52d 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -442,6 +442,9 @@ static Property arm_cpu_rvbar_property = static Property arm_cpu_has_el3_property = DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); +static Property arm_cpu_has_mpu_property = + DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); + static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -469,6 +472,12 @@ static void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, &error_abort); } + + if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) { + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, + &error_abort); + } + } static void arm_cpu_finalizefn(Object *obj) @@ -551,6 +560,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->id_aa64pfr0 &= ~0xf000; } + if (!cpu->has_mpu) { + unset_feature(env, ARM_FEATURE_MPU); + } + register_cp_regs_for_features(cpu); arm_cpu_register_gdb_regs_for_features(cpu);