| Message ID | 62798fbe9c200da3e0c870601ed9162b1c3a50a5.1660746880.git.balaton@eik.bme.hu |
|---|---|
| State | New |
| Headers | show |
| Series | QOMify PPC4xx devices and minor clean ups | expand |
On 8/17/22 17:08, BALATON Zoltan wrote: > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/ppc/ppc405_uc.c | 5 +++-- > hw/ppc/ppc440_bamboo.c | 27 ++++++++++++++---------- > hw/ppc/ppc440_uc.c | 3 ++- > hw/ppc/ppc4xx_devs.c | 48 +++++++++++++++++++++++------------------- > hw/ppc/ppc4xx_pci.c | 31 +++++++++++++++++---------- > 5 files changed, 67 insertions(+), 47 deletions(-) > > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index d541134632..6296130936 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -540,10 +540,11 @@ static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) > > mask = 0x00008000; > for (i = 0; i < 5; i++) { > - if (gpt->is & gpt->im & mask) > + if (gpt->is & gpt->im & mask) { > qemu_irq_raise(gpt->irqs[i]); > - else > + } else { > qemu_irq_lower(gpt->irqs[i]); > + } > mask = mask >> 1; > } > } > diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c > index b14a9ef776..ea945a1c99 100644 > --- a/hw/ppc/ppc440_bamboo.c > +++ b/hw/ppc/ppc440_bamboo.c > @@ -84,27 +84,30 @@ static int bamboo_load_device_tree(hwaddr addr, > > ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, > sizeof(mem_reg_property)); > - if (ret < 0) > + if (ret < 0) { > fprintf(stderr, "couldn't set /memory/reg\n"); > - > + } > ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", > initrd_base); > - if (ret < 0) > + if (ret < 0) { > fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); > - > + } > ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", > (initrd_base + initrd_size)); > - if (ret < 0) > + if (ret < 0) { > fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); > - > + } > ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", > kernel_cmdline); > - if (ret < 0) > + if (ret < 0) { > fprintf(stderr, "couldn't set /chosen/bootargs\n"); > + } > > - /* Copy data from the host device tree into the guest. Since the guest can > + /* > + * Copy data from the host device tree into the guest. Since the guest can > * directly access the timebase without host involvement, we must expose > - * the correct frequencies. */ > + * the correct frequencies. > + */ > if (kvm_enabled()) { > tb_freq = kvmppc_get_tbfreq(); > clock_freq = kvmppc_get_clockfreq(); > @@ -246,8 +249,10 @@ static void bamboo_init(MachineState *machine) > if (pcibus) { > /* Register network interfaces. */ > for (i = 0; i < nb_nics; i++) { > - /* There are no PCI NICs on the Bamboo board, but there are > - * PCI slots, so we can pick whatever default model we want. */ > + /* > + * There are no PCI NICs on the Bamboo board, but there are > + * PCI slots, so we can pick whatever default model we want. > + */ > pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); > } > } > diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c > index 11fdb88c22..53e981ddf4 100644 > --- a/hw/ppc/ppc440_uc.c > +++ b/hw/ppc/ppc440_uc.c > @@ -1028,7 +1028,8 @@ void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) > > /*****************************************************************************/ > /* PCI Express controller */ > -/* FIXME: This is not complete and does not work, only implemented partially > +/* > + * FIXME: This is not complete and does not work, only implemented partially > * to allow firmware and guests to find an empty bus. Cards should use PCI. > */ > #include "hw/pci/pcie_host.h" > diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c > index 27ebbb2ffc..ce38ae65e6 100644 > --- a/hw/ppc/ppc4xx_devs.c > +++ b/hw/ppc/ppc4xx_devs.c > @@ -65,12 +65,12 @@ enum { > SDRAM0_CFGDATA = 0x011, > }; > > -/* XXX: TOFIX: some patches have made this code become inconsistent: > +/* > + * XXX: TOFIX: some patches have made this code become inconsistent: > * there are type inconsistencies, mixing hwaddr, target_ulong > * and uint32_t > */ > -static uint32_t sdram_bcr (hwaddr ram_base, > - hwaddr ram_size) > +static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) > { > uint32_t bcr; > > @@ -113,16 +113,17 @@ static inline hwaddr sdram_base(uint32_t bcr) > return bcr & 0xFF800000; > } > > -static target_ulong sdram_size (uint32_t bcr) > +static target_ulong sdram_size(uint32_t bcr) > { > target_ulong size; > int sh; > > sh = (bcr >> 17) & 0x7; > - if (sh == 7) > + if (sh == 7) { > size = -1; > - else > + } else { > size = (4 * MiB) << sh; > + } > > return size; > } > @@ -153,7 +154,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, > } > } > > -static void sdram_map_bcr (ppc4xx_sdram_t *sdram) > +static void sdram_map_bcr(ppc4xx_sdram_t *sdram) > { > int i; > > @@ -167,7 +168,7 @@ static void sdram_map_bcr (ppc4xx_sdram_t *sdram) > } > } > > -static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) > +static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) > { > int i; > > @@ -179,7 +180,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) > } > } > > -static uint32_t dcr_read_sdram (void *opaque, int dcrn) > +static uint32_t dcr_read_sdram(void *opaque, int dcrn) > { > ppc4xx_sdram_t *sdram; > uint32_t ret; > @@ -247,7 +248,7 @@ static uint32_t dcr_read_sdram (void *opaque, int dcrn) > return ret; > } > > -static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) > +static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) > { > ppc4xx_sdram_t *sdram; > > @@ -280,10 +281,11 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) > sdram_unmap_bcr(sdram); > sdram->status |= 0x80000000; > } > - if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) > + if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { > sdram->status |= 0x40000000; > - else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) > + } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { > sdram->status &= ~0x40000000; > + } > sdram->cfg = val; > break; > case 0x24: /* SDRAM_STATUS */ > @@ -315,10 +317,11 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) > break; > case 0x98: /* SDRAM_ECCESR */ > val &= 0xFFF0F000; > - if (sdram->eccesr == 0 && val != 0) > + if (sdram->eccesr == 0 && val != 0) { > qemu_irq_raise(sdram->irq); > - else if (sdram->eccesr != 0 && val == 0) > + } else if (sdram->eccesr != 0 && val == 0) { > qemu_irq_lower(sdram->irq); > + } > sdram->eccesr = val; > break; > default: /* Error */ > @@ -328,7 +331,7 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) > } > } > > -static void sdram_reset (void *opaque) > +static void sdram_reset(void *opaque) > { > ppc4xx_sdram_t *sdram; > > @@ -348,11 +351,11 @@ static void sdram_reset (void *opaque) > sdram->cfg = 0x00800000; > } > > -void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, > - MemoryRegion *ram_memories, > - hwaddr *ram_bases, > - hwaddr *ram_sizes, > - int do_init) > +void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, > + MemoryRegion *ram_memories, > + hwaddr *ram_bases, > + hwaddr *ram_sizes, > + int do_init) > { > ppc4xx_sdram_t *sdram; > > @@ -371,8 +374,9 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, > sdram, &dcr_read_sdram, &dcr_write_sdram); > ppc_dcr_register(env, SDRAM0_CFGDATA, > sdram, &dcr_read_sdram, &dcr_write_sdram); > - if (do_init) > + if (do_init) { > sdram_map_bcr(sdram); > + } > } > > /* > @@ -429,7 +433,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, > } > error_report("at most %d bank%s of %s MiB each supported", > nr_banks, nr_banks == 1 ? "" : "s", s->str); > - error_printf("Possible valid RAM size: %" PRIi64 " MiB \n", > + error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", > used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); > > g_string_free(s, true); > diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c > index 5df97e6d15..8642b96455 100644 > --- a/hw/ppc/ppc4xx_pci.c > +++ b/hw/ppc/ppc4xx_pci.c > @@ -16,8 +16,10 @@ > * Authors: Hollis Blanchard <hollisb@us.ibm.com> > */ > > -/* This file implements emulation of the 32-bit PCI controller found in some > - * 4xx SoCs, such as the 440EP. */ > +/* > + * This file implements emulation of the 32-bit PCI controller found in some > + * 4xx SoCs, such as the 440EP. > + */ > > #include "qemu/osdep.h" > #include "qemu/log.h" > @@ -65,8 +67,10 @@ struct PPC4xxPCIState { > #define PCIC0_CFGADDR 0x0 > #define PCIC0_CFGDATA 0x4 > > -/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to > - * PCI accesses. */ > +/* > + * PLB Memory Map (PMM) registers specify which PLB addresses are translated to > + * PCI accesses. > + */ > #define PCIL0_PMM0LA 0x0 > #define PCIL0_PMM0MA 0x4 > #define PCIL0_PMM0PCILA 0x8 > @@ -80,8 +84,10 @@ struct PPC4xxPCIState { > #define PCIL0_PMM2PCILA 0x28 > #define PCIL0_PMM2PCIHA 0x2c > > -/* PCI Target Map (PTM) registers specify which PCI addresses are translated to > - * PLB accesses. */ > +/* > + * PCI Target Map (PTM) registers specify which PCI addresses are translated to > + * PLB accesses. > + */ > #define PCIL0_PTM1MS 0x30 > #define PCIL0_PTM1LA 0x34 > #define PCIL0_PTM2MS 0x38 > @@ -96,9 +102,10 @@ static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset, > { > struct PPC4xxPCIState *pci = opaque; > > - /* We ignore all target attempts at PCI configuration, effectively > - * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ > - > + /* > + * We ignore all target attempts at PCI configuration, effectively > + * assuming a bidirectional 1:1 mapping of PLB and PCI space. > + */ > switch (offset) { > case PCIL0_PMM0LA: > pci->pmm[0].la = value; > @@ -243,8 +250,10 @@ static void ppc4xx_pci_reset(void *opaque) > memset(pci->ptm, 0, sizeof(pci->ptm)); > } > > -/* On Bamboo, all pins from each slot are tied to a single board IRQ. This > - * may need further refactoring for other boards. */ > +/* > + * On Bamboo, all pins from each slot are tied to a single board IRQ. > + * This may need further refactoring for other boards. > + */ > static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) > { > int slot = PCI_SLOT(pci_dev->devfn);
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index d541134632..6296130936 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -540,10 +540,11 @@ static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) mask = 0x00008000; for (i = 0; i < 5; i++) { - if (gpt->is & gpt->im & mask) + if (gpt->is & gpt->im & mask) { qemu_irq_raise(gpt->irqs[i]); - else + } else { qemu_irq_lower(gpt->irqs[i]); + } mask = mask >> 1; } } diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b14a9ef776..ea945a1c99 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -84,27 +84,30 @@ static int bamboo_load_device_tree(hwaddr addr, ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, sizeof(mem_reg_property)); - if (ret < 0) + if (ret < 0) { fprintf(stderr, "couldn't set /memory/reg\n"); - + } ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base); - if (ret < 0) + if (ret < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); - + } ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", (initrd_base + initrd_size)); - if (ret < 0) + if (ret < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); - + } ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline); - if (ret < 0) + if (ret < 0) { fprintf(stderr, "couldn't set /chosen/bootargs\n"); + } - /* Copy data from the host device tree into the guest. Since the guest can + /* + * Copy data from the host device tree into the guest. Since the guest can * directly access the timebase without host involvement, we must expose - * the correct frequencies. */ + * the correct frequencies. + */ if (kvm_enabled()) { tb_freq = kvmppc_get_tbfreq(); clock_freq = kvmppc_get_clockfreq(); @@ -246,8 +249,10 @@ static void bamboo_init(MachineState *machine) if (pcibus) { /* Register network interfaces. */ for (i = 0; i < nb_nics; i++) { - /* There are no PCI NICs on the Bamboo board, but there are - * PCI slots, so we can pick whatever default model we want. */ + /* + * There are no PCI NICs on the Bamboo board, but there are + * PCI slots, so we can pick whatever default model we want. + */ pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL); } } diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 11fdb88c22..53e981ddf4 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -1028,7 +1028,8 @@ void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) /*****************************************************************************/ /* PCI Express controller */ -/* FIXME: This is not complete and does not work, only implemented partially +/* + * FIXME: This is not complete and does not work, only implemented partially * to allow firmware and guests to find an empty bus. Cards should use PCI. */ #include "hw/pci/pcie_host.h" diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 27ebbb2ffc..ce38ae65e6 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -65,12 +65,12 @@ enum { SDRAM0_CFGDATA = 0x011, }; -/* XXX: TOFIX: some patches have made this code become inconsistent: +/* + * XXX: TOFIX: some patches have made this code become inconsistent: * there are type inconsistencies, mixing hwaddr, target_ulong * and uint32_t */ -static uint32_t sdram_bcr (hwaddr ram_base, - hwaddr ram_size) +static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) { uint32_t bcr; @@ -113,16 +113,17 @@ static inline hwaddr sdram_base(uint32_t bcr) return bcr & 0xFF800000; } -static target_ulong sdram_size (uint32_t bcr) +static target_ulong sdram_size(uint32_t bcr) { target_ulong size; int sh; sh = (bcr >> 17) & 0x7; - if (sh == 7) + if (sh == 7) { size = -1; - else + } else { size = (4 * MiB) << sh; + } return size; } @@ -153,7 +154,7 @@ static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, } } -static void sdram_map_bcr (ppc4xx_sdram_t *sdram) +static void sdram_map_bcr(ppc4xx_sdram_t *sdram) { int i; @@ -167,7 +168,7 @@ static void sdram_map_bcr (ppc4xx_sdram_t *sdram) } } -static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) +static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) { int i; @@ -179,7 +180,7 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram) } } -static uint32_t dcr_read_sdram (void *opaque, int dcrn) +static uint32_t dcr_read_sdram(void *opaque, int dcrn) { ppc4xx_sdram_t *sdram; uint32_t ret; @@ -247,7 +248,7 @@ static uint32_t dcr_read_sdram (void *opaque, int dcrn) return ret; } -static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) +static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) { ppc4xx_sdram_t *sdram; @@ -280,10 +281,11 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) sdram_unmap_bcr(sdram); sdram->status |= 0x80000000; } - if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) + if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { sdram->status |= 0x40000000; - else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) + } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { sdram->status &= ~0x40000000; + } sdram->cfg = val; break; case 0x24: /* SDRAM_STATUS */ @@ -315,10 +317,11 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) break; case 0x98: /* SDRAM_ECCESR */ val &= 0xFFF0F000; - if (sdram->eccesr == 0 && val != 0) + if (sdram->eccesr == 0 && val != 0) { qemu_irq_raise(sdram->irq); - else if (sdram->eccesr != 0 && val == 0) + } else if (sdram->eccesr != 0 && val == 0) { qemu_irq_lower(sdram->irq); + } sdram->eccesr = val; break; default: /* Error */ @@ -328,7 +331,7 @@ static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val) } } -static void sdram_reset (void *opaque) +static void sdram_reset(void *opaque) { ppc4xx_sdram_t *sdram; @@ -348,11 +351,11 @@ static void sdram_reset (void *opaque) sdram->cfg = 0x00800000; } -void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, - MemoryRegion *ram_memories, - hwaddr *ram_bases, - hwaddr *ram_sizes, - int do_init) +void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, + MemoryRegion *ram_memories, + hwaddr *ram_bases, + hwaddr *ram_sizes, + int do_init) { ppc4xx_sdram_t *sdram; @@ -371,8 +374,9 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) + if (do_init) { sdram_map_bcr(sdram); + } } /* @@ -429,7 +433,7 @@ void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, } error_report("at most %d bank%s of %s MiB each supported", nr_banks, nr_banks == 1 ? "" : "s", s->str); - error_printf("Possible valid RAM size: %" PRIi64 " MiB \n", + error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); g_string_free(s, true); diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c index 5df97e6d15..8642b96455 100644 --- a/hw/ppc/ppc4xx_pci.c +++ b/hw/ppc/ppc4xx_pci.c @@ -16,8 +16,10 @@ * Authors: Hollis Blanchard <hollisb@us.ibm.com> */ -/* This file implements emulation of the 32-bit PCI controller found in some - * 4xx SoCs, such as the 440EP. */ +/* + * This file implements emulation of the 32-bit PCI controller found in some + * 4xx SoCs, such as the 440EP. + */ #include "qemu/osdep.h" #include "qemu/log.h" @@ -65,8 +67,10 @@ struct PPC4xxPCIState { #define PCIC0_CFGADDR 0x0 #define PCIC0_CFGDATA 0x4 -/* PLB Memory Map (PMM) registers specify which PLB addresses are translated to - * PCI accesses. */ +/* + * PLB Memory Map (PMM) registers specify which PLB addresses are translated to + * PCI accesses. + */ #define PCIL0_PMM0LA 0x0 #define PCIL0_PMM0MA 0x4 #define PCIL0_PMM0PCILA 0x8 @@ -80,8 +84,10 @@ struct PPC4xxPCIState { #define PCIL0_PMM2PCILA 0x28 #define PCIL0_PMM2PCIHA 0x2c -/* PCI Target Map (PTM) registers specify which PCI addresses are translated to - * PLB accesses. */ +/* + * PCI Target Map (PTM) registers specify which PCI addresses are translated to + * PLB accesses. + */ #define PCIL0_PTM1MS 0x30 #define PCIL0_PTM1LA 0x34 #define PCIL0_PTM2MS 0x38 @@ -96,9 +102,10 @@ static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset, { struct PPC4xxPCIState *pci = opaque; - /* We ignore all target attempts at PCI configuration, effectively - * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ - + /* + * We ignore all target attempts at PCI configuration, effectively + * assuming a bidirectional 1:1 mapping of PLB and PCI space. + */ switch (offset) { case PCIL0_PMM0LA: pci->pmm[0].la = value; @@ -243,8 +250,10 @@ static void ppc4xx_pci_reset(void *opaque) memset(pci->ptm, 0, sizeof(pci->ptm)); } -/* On Bamboo, all pins from each slot are tied to a single board IRQ. This - * may need further refactoring for other boards. */ +/* + * On Bamboo, all pins from each slot are tied to a single board IRQ. + * This may need further refactoring for other boards. + */ static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) { int slot = PCI_SLOT(pci_dev->devfn);
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- hw/ppc/ppc405_uc.c | 5 +++-- hw/ppc/ppc440_bamboo.c | 27 ++++++++++++++---------- hw/ppc/ppc440_uc.c | 3 ++- hw/ppc/ppc4xx_devs.c | 48 +++++++++++++++++++++++------------------- hw/ppc/ppc4xx_pci.c | 31 +++++++++++++++++---------- 5 files changed, 67 insertions(+), 47 deletions(-)