diff mbox series

[v7,3/7] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV

Message ID 5cf3590d5354b9be53d596a44023fdbe669c749b.1539428198.git.noring@nocrew.org
State New
Headers show
Series target/mips: Limited support for the R5900 | expand

Commit Message

Fredrik Noring Oct. 13, 2018, 11:10 a.m. UTC 
The R5900 is taken to be MIPS III with certain modifications. From
MIPS IV it implements the instructions MOVN, MOVZ and PREF.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index a32e021745..9d9be199e4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -22422,7 +22422,7 @@  static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
     case OPC_MOVN:         /* Conditional move */
     case OPC_MOVZ:
         check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
-                   INSN_LOONGSON2E | INSN_LOONGSON2F);
+                   INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
         gen_cond_move(ctx, op1, rd, rs, rt);
         break;
     case OPC_MFHI:          /* Move from HI/LO */
@@ -25006,7 +25006,8 @@  static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_PREF:
         check_insn_opc_removed(ctx, ISA_MIPS32R6);
-        check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+        check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+                   INSN_R5900);
         /* Treat as NOP. */
         break;