@@ -2720,6 +2720,28 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos)
return 0;
}
+static int vfio_setup_aer(VFIOPCIDevice *vdev, uint8_t cap_ver,
+ int pos, uint16_t size)
+{
+ PCIDevice *pdev = &vdev->pdev;
+ uint8_t *exp_cap = pdev->config + pdev->exp.exp_cap;
+ uint32_t severity;
+ int ret;
+
+ pdev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
+ ret = pcie_aer_init(pdev, cap_ver, pos, size);
+ if (ret) {
+ return ret;
+ }
+
+ /* load physical registers */
+ severity = vfio_pci_read_config(pdev,
+ pdev->exp.aer_cap + PCI_ERR_UNCOR_SEVER, 4);
+ pci_long_test_and_clear_mask(exp_cap + PCI_ERR_UNCOR_SEVER, ~severity);
+
+ return 0;
+}
+
static int vfio_add_ext_cap(VFIOPCIDevice *vdev, const uint8_t *config,
uint16_t pos)
{
@@ -2742,7 +2764,18 @@ static int vfio_add_ext_cap(VFIOPCIDevice *vdev, const uint8_t *config,
*/
size = vfio_ext_cap_max_size(config, pos);
- pcie_add_capability(pdev, cap_id, cap_ver, pos, size);
+ switch (cap_id) {
+ case PCI_EXT_CAP_ID_ERR:
+ ret = vfio_setup_aer(vdev, cap_ver, pos, size);
+ if (ret) {
+ return ret;
+ }
+ break;
+ default:
+ pcie_add_capability(pdev, cap_id, cap_ver, pos, size);
+ break;
+ }
+
if (pos == PCI_CONFIG_SPACE_SIZE) {
/* Begin the rebuild, we should set the next offset zero. */
pci_set_long(pdev->config + pos, PCI_EXT_CAP(cap_id, cap_ver, 0));
Calling pcie_aer_init to initilize aer related registers for vfio device, then reload physical related registers to expose device capability. Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> --- hw/vfio/pci.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-)