From patchwork Sun Jun 7 09:15:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 481701 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 9E788140187 for ; Sun, 7 Jun 2015 19:15:52 +1000 (AEST) Received: from localhost ([::1]:53807 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z1WgF-0000pd-Fn for incoming@patchwork.ozlabs.org; Sun, 07 Jun 2015 05:15:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z1Wfw-0000ZF-8f for qemu-devel@nongnu.org; Sun, 07 Jun 2015 05:15:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z1Wfr-0003Zd-5q for qemu-devel@nongnu.org; Sun, 07 Jun 2015 05:15:28 -0400 Received: from mout.web.de ([212.227.17.12]:62612) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z1Wfq-0003ZI-SE for qemu-devel@nongnu.org; Sun, 07 Jun 2015 05:15:23 -0400 Received: from md1f2u6c.ww002.siemens.net ([95.157.58.223]) by smtp.web.de (mrweb101) with ESMTPSA (Nemesis) id 0MHowb-1Z2tZy0a69-003bZM; Sun, 07 Jun 2015 11:15:11 +0200 Message-ID: <55740B9C.6030107@web.de> Date: Sun, 07 Jun 2015 11:15:08 +0200 From: Jan Kiszka User-Agent: Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 MIME-Version: 1.0 To: Eduardo Habkost , Paolo Bonzini X-Provags-ID: V03:K0:g+cnZOSDot6wmCN1PG1VOHWm+1emyR7Jt48PeDfc89cMTtv4N+x 3jSvOkBbe06ZUrY1kFdY9WuTyV561qcxx6IrHkoTAnAcDKkJnbzvxRPPOD1loXHwPQ//k8w pUedP1JdmVVqz0X3gfPCVX/t/jf09jwyPkFzA/iubaWrIwMQ2uejA7bvRdX4Dofgw/fb/KQ kM9b4r9f7K1XhMYjR2vPg== X-UI-Out-Filterresults: notjunk:1; V01:K0:A9KFAbvAp7c=:e556ehqfUR8t32yUcjeyxK pukOIx5a03E0SI0LcnQ7l+1jfQrRPDacxqdMWVf1EXxx5TVe6D0lm6R/o+Mr70hjDDOQ5guIs 1N+YUeeD6oLQc9Xdu4z9ZGl5b+oAZ21Jqe0uE8XaPSYAwiAuRvQzqqbF8+0ZT56EbTDYVv3qz +aDSfUO+GrHZJ45RwCYnUiR9ZuQ6k5vZjgxDfgV1uy5G0bWM2SlRqDLq00/64O+IU1NuMSmCD yFUDT6TrTPWym/l29+pySUTfxy7TM7Yb+9rdf6Q5asfxabyuxeL5oh5u6nt/gRbQPHm0uwPB7 ClNM17aXMGj1hpmyKdQBV7h2HZJBykhtNCp5hn34BuBR+CM199KldQKx4j3gjsImD/iNsJMh9 xvxlYkZd5nl/2hwtr4eHcZWi6OXo2bXUU+natOyp2c2NR1H6mkC+VUj1jLnRZ5gPj57IcTa9g WWsoh3kKARMbd2X9FmFbdKXai4h5jT3nxWbPHC/3pxsIgfkMulke1WuOfa21TXvrSoSw8iDry Yhr3E71XPaHTgg6K2WRGKAUfykyw3K55tFsldipn4aVveDcSo0Q7gANEULWGUTGRghErz7yMu uBoe1hJGFBf9Ybx7XiG4UpbtIdmqxP2YtTW9tDUxc46oCqpHTrvM4qZ9rhDuj/pYBKQ4e4R3q jt4zL5jYrCpTxVoJ2esTA5BGuX3Zuui6ogC/WUY9zAGv3wg== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 212.227.17.12 Cc: qemu-devel , kvm , "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v5] i386: Introduce ARAT CPU feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Jan Kiszka ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Signed-off-by: Jan Kiszka Acked-by: Paolo Bonzini Acked-by: Michael S. Tsirkin Reviewed-by: Eduardo Habkost --- Changes in v5: - rebased over master include/hw/i386/pc.h | 7 ++++++- target-i386/cpu.c | 33 ++++++++++++++++++++++++++++++++- target-i386/cpu.h | 3 +++ target-i386/kvm.c | 2 ++ 4 files changed, 43 insertions(+), 2 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index bec6de1..3b0b30f 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -294,7 +294,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_3 \ - HW_COMPAT_2_3 + HW_COMPAT_2_3 \ + {\ + .driver = TYPE_X86_CPU,\ + .property = "arat",\ + .value = "off",\ + }, #define PC_COMPAT_2_2 \ PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 99ad551..b5b9fc2 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -284,6 +284,17 @@ static const char *cpuid_xsave_feature_name[] = { NULL, NULL, NULL, NULL, }; +static const char *cpuid_6_feature_name[] = { + NULL, NULL, "arat", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, +}; + #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) @@ -339,6 +350,7 @@ static const char *cpuid_xsave_feature_name[] = { CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED */ #define TCG_APM_FEATURES 0 +#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT typedef struct FeatureWordInfo { @@ -408,6 +420,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .cpuid_reg = R_EAX, .tcg_features = 0, }, + [FEAT_6_EAX] = { + .feat_names = cpuid_6_feature_name, + .cpuid_eax = 6, .cpuid_reg = R_EAX, + .tcg_features = TCG_6_EAX_FEATURES, + }, }; typedef struct X86RegisterInfo32 { @@ -1001,6 +1018,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, @@ -1030,6 +1049,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E312xx (Sandy Bridge)", }, @@ -1062,6 +1083,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_LAHF_LM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", }, @@ -1096,6 +1119,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell, no TSX)", }, { @@ -1130,6 +1155,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_RTM, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Haswell)", }, @@ -1166,6 +1193,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell, no TSX)", }, @@ -1202,6 +1231,8 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_7_0_EBX_SMAP, .features[FEAT_XSAVE] = CPUID_XSAVE_XSAVEOPT, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, .xlevel = 0x8000000A, .model_id = "Intel Core Processor (Broadwell)", }, @@ -2358,7 +2389,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, break; case 6: /* Thermal and Power Leaf */ - *eax = 0; + *eax = env->features[FEAT_6_EAX]; *ebx = 0; *ecx = 0; *edx = 0; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 26182bd..074a9c9 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -412,6 +412,7 @@ typedef enum FeatureWord { FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */ FEAT_SVM, /* CPUID[8000_000A].EDX */ FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */ + FEAT_6_EAX, /* CPUID[6].EAX */ FEATURE_WORDS, } FeatureWord; @@ -577,6 +578,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_XSAVE_XGETBV1 (1U << 2) #define CPUID_XSAVE_XSAVES (1U << 3) +#define CPUID_6_EAX_ARAT (1U << 2) + /* CPUID[0x80000007].EDX flags: */ #define CPUID_APM_INVTSC (1U << 8) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index ca2da84..d7bd205 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -233,6 +233,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, if (!kvm_irqchip_in_kernel()) { ret &= ~CPUID_EXT_X2APIC; } + } else if (function == 6 && reg == R_EAX) { + ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: