From patchwork Mon Dec 8 21:19:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 418876 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5048A1400B7 for ; Tue, 9 Dec 2014 08:19:50 +1100 (AEDT) Received: from localhost ([::1]:36203 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xy5ie-0004SI-8y for incoming@patchwork.ozlabs.org; Mon, 08 Dec 2014 16:19:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xy5iG-000494-Ej for qemu-devel@nongnu.org; Mon, 08 Dec 2014 16:19:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xy5iA-0000aL-6c for qemu-devel@nongnu.org; Mon, 08 Dec 2014 16:19:24 -0500 Received: from mx1.redhat.com ([209.132.183.28]:56597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xy5i9-0000Zl-Ur for qemu-devel@nongnu.org; Mon, 08 Dec 2014 16:19:18 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id sB8LJFMt029668 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 8 Dec 2014 16:19:15 -0500 Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-21.ams2.redhat.com [10.36.116.21]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id sB8LJ2a6004059; Mon, 8 Dec 2014 16:19:03 -0500 Message-ID: <548615CE.10100@redhat.com> Date: Mon, 08 Dec 2014 22:19:10 +0100 From: Laszlo Ersek User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-Version: 1.0 To: Peter Maydell References: <1417366783-14242-1-git-send-email-lersek@redhat.com> <5485AF57.6050902@redhat.com> <5485FE8A.7040309@redhat.com> In-Reply-To: <5485FE8A.7040309@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: Drew Jones , Ard Biesheuvel , QEMU Developers , Christoffer Dall , "Richard W.M. Jones" Subject: Re: [Qemu-devel] [PATCH v2] arm: add fw_cfg to "virt" board X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On 12/08/14 20:39, Laszlo Ersek wrote: > On 12/08/14 15:41, Peter Maydell wrote: >> On 8 December 2014 at 14:01, Laszlo Ersek wrote: >>> Peter, can we introduce a second, 64-bit wide, data register, for >>> fw_cfg? (Or even two -- Drew suggested the LDP instruction for the guest.) >> >> I don't have an in-principle objection. I do require that >> whatever mechanism we provide is usable by 32 bit guests >> as well as 64 bit guests. > > The idea is that in the following: > > fw_cfg_data_mem_read() > fw_cfg_read() > > fw_cfg_data_mem_read() doesn't care about either "addr" or "size", which > happens to be the best for the current problem. > > According to the documentation on "MemoryRegionOps" in > "include/exec/memory.h" (and also to my testing in practice), if you set > .valid.max_access_size to something large (definitely up to 8, but maybe > even up to 16?), but keep .impl.max_access_size at something smaller, > then "memory.c" will split up the access for you automatically. > (Ultimately turning the bigger access to several sequential calls to > fw_cfg_read(), which happens to be correct.) > > So, if a 32-bit guest never "submits" an access wider than 32-bit, then > that's the largest that "memory.c" will slice and dice. > >> You'll also want the access instruction >> to be one where the hardware provides instruction syndrome information >> to KVM about the faulting load/store, > > Yes, I definitely remembered this; I just didn't know how to name it > precisely. > >> which means you can only use >> AArch64 loads and stores of a single general-purpose register, and >> AArch32 instructions LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, >> LDRSB, LDRSBT, LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, >> STRB, STLB, or STRBT. >> >> Note that this rules out LDP. > > Yes, I was concerned about this (Drew can confirm :)) Thank you very > much for making this clear; this will definitely help with the guest > code. Also we don't have to figure out if .valid.max_access_size=16 > would work at all. > >> We also need to make sure it works with TCG QEMU. (64-bit access >> to devices is something we've needed previously in ARM QEMU, so >> though in theory it should work it would need testing.) > > (Factoring in the typo correction from your next mail:) > > Good point. I just tested TCG. While the speedup is similar, the data > that is transferred looks corrupt. Okay, TCG is not the culprit, it seems to work okay. I messed up the memory region registration in the previous patch. On x86_64 the 8-byte access is broken up into two 4-byte accesses, and the second one of those is not accepted as a valid access, and it qualifies as an unassigned read. So the following in addition makes it work on TCG (x86_64) too: ----------------- ----------------- It affects the memory_region_init_io() call in fw_cfg_initfn(). I hope to submit a small v3 series soon. Thanks, Laszlo diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 7147fea..c2bc44c 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -31,7 +31,7 @@ #include "qemu/config-file.h" #define FW_CFG_SIZE 2 -#define FW_CFG_DATA_SIZE 1 +#define FW_CFG_DATA_SIZE 8 #define TYPE_FW_CFG "fw_cfg" #define FW_CFG_NAME "fw_cfg" #define FW_CFG_PATH "/machine/" FW_CFG_NAME