From patchwork Wed Jun 6 13:31:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 925853 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=2001:4830:134:3::11; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=eik.bme.hu Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4119Hh6w2rz9s01 for ; Wed, 6 Jun 2018 23:58:23 +1000 (AEST) Received: from localhost ([::1]:52595 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYxB-0008RR-09 for incoming@patchwork.ozlabs.org; Wed, 06 Jun 2018 09:58:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40178) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fQYwW-0008Q8-5B for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fQYwU-0000Wy-DW for qemu-devel@nongnu.org; Wed, 06 Jun 2018 09:57:40 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:44633) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fQYwU-0000Vk-0D; Wed, 06 Jun 2018 09:57:38 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 9C4CE7456B4; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 013807456B5; Wed, 6 Jun 2018 15:57:28 +0200 (CEST) Message-Id: <53f9d0b04374a3f4449af65ce01bd68dbe757ab5.1528291908.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Wed, 06 Jun 2018 15:31:48 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH v2 1/8] ppc4xx_i2c: Clean up and improve error logging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Make it more readable by converting register indexes to decimal (avoids lot of superfluous 0x0) and distinguish errors caused by accessing non-existent vs. unimplemented registers. No functional change. Signed-off-by: BALATON Zoltan --- hw/i2c/ppc4xx_i2c.c | 94 +++++++++++++++++++++++++++++------------------------ 1 file changed, 51 insertions(+), 43 deletions(-) diff --git a/hw/i2c/ppc4xx_i2c.c b/hw/i2c/ppc4xx_i2c.c index ab64d19..d1936db 100644 --- a/hw/i2c/ppc4xx_i2c.c +++ b/hw/i2c/ppc4xx_i2c.c @@ -31,7 +31,7 @@ #include "hw/hw.h" #include "hw/i2c/ppc4xx_i2c.h" -#define PPC4xx_I2C_MEM_SIZE 0x12 +#define PPC4xx_I2C_MEM_SIZE 18 #define IIC_CNTL_PT (1 << 0) #define IIC_CNTL_READ (1 << 1) @@ -70,7 +70,7 @@ static void ppc4xx_i2c_reset(DeviceState *s) i2c->intrmsk = 0; i2c->xfrcnt = 0; i2c->xtcntlss = 0; - i2c->directcntl = 0x0f; + i2c->directcntl = 0xf; i2c->intr = 0; } @@ -85,7 +85,7 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size) uint64_t ret; switch (addr) { - case 0x00: + case 0: ret = i2c->mdata; if (ppc4xx_i2c_is_master(i2c)) { ret = 0xff; @@ -139,58 +139,62 @@ static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size) TYPE_PPC4xx_I2C, __func__); } break; - case 0x02: + case 2: ret = i2c->sdata; break; - case 0x04: + case 4: ret = i2c->lmadr; break; - case 0x05: + case 5: ret = i2c->hmadr; break; - case 0x06: + case 6: ret = i2c->cntl; break; - case 0x07: + case 7: ret = i2c->mdcntl; break; - case 0x08: + case 8: ret = i2c->sts; break; - case 0x09: + case 9: ret = i2c->extsts; break; - case 0x0A: + case 10: ret = i2c->lsadr; break; - case 0x0B: + case 11: ret = i2c->hsadr; break; - case 0x0C: + case 12: ret = i2c->clkdiv; break; - case 0x0D: + case 13: ret = i2c->intrmsk; break; - case 0x0E: + case 14: ret = i2c->xfrcnt; break; - case 0x0F: + case 15: ret = i2c->xtcntlss; break; - case 0x10: + case 16: ret = i2c->directcntl; break; - case 0x11: + case 17: ret = i2c->intr; break; default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" - HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); + if (addr < PPC4xx_I2C_MEM_SIZE) { + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" + HWADDR_PRIx "\n", __func__, addr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" + HWADDR_PRIx "\n", __func__, addr); + } ret = 0; break; } - return ret; } @@ -200,7 +204,7 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, PPC4xxI2CState *i2c = opaque; switch (addr) { - case 0x00: + case 0: i2c->mdata = value; if (!i2c_bus_busy(i2c->bus)) { /* assume we start a write transfer */ @@ -225,19 +229,19 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, } } break; - case 0x02: + case 2: i2c->sdata = value; break; - case 0x04: + case 4: i2c->lmadr = value; if (i2c_bus_busy(i2c->bus)) { i2c_end_transfer(i2c->bus); } break; - case 0x05: + case 5: i2c->hmadr = value; break; - case 0x06: + case 6: i2c->cntl = value; if (i2c->cntl & IIC_CNTL_PT) { if (i2c->cntl & IIC_CNTL_READ) { @@ -263,32 +267,31 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, } } break; - case 0x07: - i2c->mdcntl = value & 0xDF; + case 7: + i2c->mdcntl = value & 0xdf; break; - case 0x08: - i2c->sts &= ~(value & 0x0A); + case 8: + i2c->sts &= ~(value & 0xa); break; - case 0x09: - i2c->extsts &= ~(value & 0x8F); + case 9: + i2c->extsts &= ~(value & 0x8f); break; - case 0x0A: + case 10: i2c->lsadr = value; - /*i2c_set_slave_address(i2c->bus, i2c->lsadr);*/ break; - case 0x0B: + case 11: i2c->hsadr = value; break; - case 0x0C: + case 12: i2c->clkdiv = value; break; - case 0x0D: + case 13: i2c->intrmsk = value; break; - case 0x0E: + case 14: i2c->xfrcnt = value & 0x77; break; - case 0x0F: + case 15: if (value & IIC_XTCNTLSS_SRST) { /* Is it actually a full reset? U-Boot sets some regs before */ ppc4xx_i2c_reset(DEVICE(i2c)); @@ -296,15 +299,20 @@ static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value, } i2c->xtcntlss = value; break; - case 0x10: + case 16: i2c->directcntl = value & 0x7; break; - case 0x11: + case 17: i2c->intr = value; break; default: - qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at offset 0x%" - HWADDR_PRIx "\n", TYPE_PPC4xx_I2C, __func__, addr); + if (addr < PPC4xx_I2C_MEM_SIZE) { + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%" + HWADDR_PRIx "\n", __func__, addr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%" + HWADDR_PRIx "\n", __func__, addr); + } break; } }