From patchwork Fri May 8 00:57:38 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 469845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 747A31402A0 for ; Fri, 8 May 2015 10:58:48 +1000 (AEST) Received: from localhost ([::1]:53261 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqWco-0003pb-Gv for incoming@patchwork.ozlabs.org; Thu, 07 May 2015 20:58:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqWbr-00020j-RW for qemu-devel@nongnu.org; Thu, 07 May 2015 20:57:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YqWbn-0001k8-IQ for qemu-devel@nongnu.org; Thu, 07 May 2015 20:57:47 -0400 Received: from mail-pd0-f175.google.com ([209.85.192.175]:36453) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YqWbn-0001j8-BX for qemu-devel@nongnu.org; Thu, 07 May 2015 20:57:43 -0400 Received: by pdea3 with SMTP id a3so55874849pde.3 for ; Thu, 07 May 2015 17:57:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Wmu0lg9UytCOwQcVgyudnjTaS4I9a1gNjhKG3fiFOYg=; b=gmRZ6zBkOVNPdOO6gMRiDhUX96oy2Z8mGe7oPFX8htHQV+vjkddTnBcWHb0vqqPRlt gzu7naCExZbVY9Iug8Q8by1EiASHck3AUMkd97i//Xlb+bsIx5icpzX8IUcn0OYSp4GM 5DgoS5yE77+2BH/LXzqySqKSVjJjzLEZhhCmiGtgbYdM3woM8MCZPcTcxtPp5SY+0Hn4 T6tll8vm4NMQAYsqQfRn4O77LRUc/BoThTqkQrW6HSB4CfXh37GYyOKH9ZQbfY0su23X hFTXaOmKY69BfRhld95AP+1LPGUWPY1QsYpA9q9ZxPhJxUNKx482XbV5+aCkoeta8hl6 fVJw== X-Gm-Message-State: ALoCoQmtJhjF5tIspsnucCLOosgTTAcTpiCwpYUvllLWIzae/1WlpH9ZivSJv0e56Na2tF83lc5M X-Received: by 10.70.27.196 with SMTP id v4mr2160289pdg.122.1431046662696; Thu, 07 May 2015 17:57:42 -0700 (PDT) Received: from localhost ([149.199.62.254]) by mx.google.com with ESMTPSA id hj11sm3313165pbd.33.2015.05.07.17.57.41 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 May 2015 17:57:42 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Thu, 7 May 2015 17:57:38 -0700 Message-Id: <52a7a784b625480f5b624cb476ec42b263f79eb2.1431045878.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 2.4.0.3.ge0ccc3b.dirty In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.192.175 Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, zach.pfeffer@xilinx.com, jues@xilinx.com, ozaki.ryota@gmail.com, alistair.francis@xilinx.com, michals@xilinx.com Subject: [Qemu-devel] [PATCH target-arm v8 08/14] arm: xlnx-zynqmp: Add GEM support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell Tested-by: Alistair Francis Signed-off-by: Peter Crosthwaite --- changed since v4: Remove use of ERR_PROP_CHECK_RETURN hw/arm/xlnx-zynqmp.c | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 3 +++ 2 files changed, 38 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 1adaa46..02e53c5 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -28,6 +28,14 @@ #define GIC_DIST_ADDR 0xf9010000 #define GIC_CPU_ADDR 0xf9020000 +static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = { + 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000, +}; + +static const int gem_intr[XLNX_ZYNQMP_NUM_GEMS] = { + 57, 59, 61, 63, +}; + typedef struct XlnxZynqMPGICRegion { int region_index; uint32_t address; @@ -57,6 +65,11 @@ static void xlnx_zynqmp_init(Object *obj) object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); + + for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { + object_initialize(&s->gem[i], sizeof(s->gem[i]), TYPE_CADENCE_GEM); + qdev_set_parent_bus(DEVICE(&s->gem[i]), sysbus_get_default()); + } } static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -64,6 +77,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) XlnxZynqMPState *s = XLNX_ZYNQMP(dev); MemoryRegion *system_memory = get_system_memory(); uint8_t i; + qemu_irq gic_spi[GIC_NUM_SPI_INTR]; Error *err = NULL; qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32); @@ -127,6 +141,27 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); qdev_connect_gpio_out(DEVICE(&s->cpu[i]), 1, irq); } + + for (i = 0; i < GIC_NUM_SPI_INTR; i++) { + gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); + } + + for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { + NICInfo *nd = &nd_table[i]; + + if (nd->used) { + qemu_check_nic_model(nd, TYPE_CADENCE_GEM); + qdev_set_nic_properties(DEVICE(&s->gem[i]), nd); + } + object_property_set_bool(OBJECT(&s->gem[i]), true, "realized", &err); + if (err) { + error_propagate((errp), (err)); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem[i]), 0, gem_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem[i]), 0, + gic_spi[gem_intr[i]]); + } } static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 719bc8b..c6ccbd8 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -20,12 +20,14 @@ #include "qemu-common.h" #include "hw/arm/arm.h" #include "hw/intc/arm_gic.h" +#include "hw/net/cadence_gem.h" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ TYPE_XLNX_ZYNQMP) #define XLNX_ZYNQMP_NUM_CPUS 4 +#define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_GIC_REGIONS 2 @@ -46,6 +48,7 @@ typedef struct XlnxZynqMPState { ARMCPU cpu[XLNX_ZYNQMP_NUM_CPUS]; GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; + CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; } XlnxZynqMPState; #define XLNX_ZYNQMP_H