From patchwork Thu Oct 24 16:23:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Musta X-Patchwork-Id: 285981 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 466F42C009A for ; Fri, 25 Oct 2013 03:53:55 +1100 (EST) Received: from localhost ([::1]:55282 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZNjm-000347-5A for incoming@patchwork.ozlabs.org; Thu, 24 Oct 2013 12:26:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZNiN-0001WC-SB for qemu-devel@nongnu.org; Thu, 24 Oct 2013 12:24:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VZNi9-0003fc-Ug for qemu-devel@nongnu.org; Thu, 24 Oct 2013 12:24:51 -0400 Received: from mail-gg0-f175.google.com ([209.85.161.175]:50189) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZNi9-0003fI-PV; Thu, 24 Oct 2013 12:24:37 -0400 Received: by mail-gg0-f175.google.com with SMTP id i1so779143ggn.20 for ; Thu, 24 Oct 2013 09:24:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; bh=5Wq97MD11WTJ+vzRIUyzbZV/D0i7DPaGBzEGoVBYncE=; b=iKvXuDeoDqDm8oxs4TiCc/R2kHqmnQdMhSiZ1Ioj5Jtuf748ZAunqXtEKleUEAlmjp tlCyEpUTFXT0FvjQ13D9J0J2RDIiPTdOFHfAUK6SsnEmtDmbhMyWRQLC/dciC10a5cWR 1NVWp7x/hukMm16mKFkoqfp4Uhx7uqTMP4nf+Lwn+dE7IfPXGwmtcuydoiLY8m5Nc71S Nyn1xl3mTekdIW/22DcAPd29GlZPdwBiFzAru1N05ndQPPlXsqA9NmKb7+NP2JNyI//4 nGtmM0N/pumxXsEQuNzbS9iM5cPKaLpCWaCRqoeohgd1KM83SD9hwx+c7Mp5MtUyx+FM 1fug== X-Received: by 10.236.222.231 with SMTP id t97mr927722yhp.125.1382631842116; Thu, 24 Oct 2013 09:24:02 -0700 (PDT) Received: from [9.10.80.59] (rchp4.rochester.ibm.com. [129.42.161.36]) by mx.google.com with ESMTPSA id g14sm3621879yhb.23.2013.10.24.09.24.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 24 Oct 2013 09:24:01 -0700 (PDT) Message-ID: <5269499C.2020903@gmail.com> Date: Thu, 24 Oct 2013 11:23:56 -0500 From: Tom Musta User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.0.1 MIME-Version: 1.0 To: QEMU Developers References: <526947CA.4020504@gmail.com> In-Reply-To: <526947CA.4020504@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.161.175 Cc: Tom Musta , "qemu-ppc@nongnu.org" Subject: [Qemu-devel] [PATCH 11/19] Add VSX ISA2.06 xtdiv Instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch adds the VSX floating point test for software divide instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp, and xvtdivsp. Signed-off-by: Tom Musta Reviewed-by: Richard Henderson --- target-ppc/fpu_helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++ target-ppc/helper.h | 3 ++ target-ppc/translate.c | 6 +++++ 3 files changed, 64 insertions(+), 0 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 902cb76..0dc498c 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -2071,3 +2071,58 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ VSX_RSQRTE(xsrsqrtedp, 1, float64, f64, 1) VSX_RSQRTE(xvrsqrtedp, 2, float64, f64, 0) VSX_RSQRTE(xvrsqrtesp, 4, float32, f32, 0) + +/* VSX_TDIV - VSX floating point test for divide + * op - instruction mnemonic + * nels - number of elements (1, 2 or 4) + * tp - type (float32 or float64) + * fld - vsr_t field (f32 or f64) + * emin - minimum unbiased exponent + * emax - maximum unbiased exponent + * nbits - number of fraction bits + */ +#define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \ +void helper_##op(CPUPPCState *env, uint32_t opcode) \ +{ \ + ppc_vsr_t xa, xb; \ + int i; \ + int fe_flag = 0; \ + int fg_flag = 0; \ + \ + getVSR(xA(opcode), &xa, env); \ + getVSR(xB(opcode), &xb, env); \ + \ + for (i = 0; i < nels; i++) { \ + if (unlikely(tp##_is_infinity(xa.fld[i]) || \ + tp##_is_infinity(xb.fld[i]) || \ + tp##_is_zero(xb.fld[i]))) { \ + fe_flag = 1; \ + fg_flag = 1; \ + } else { \ + int e_a = tp##_get_unbiased_exp(xa.fld[i]); \ + int e_b = tp##_get_unbiased_exp(xb.fld[i]); \ + \ + if (unlikely(tp##_is_any_nan(xa.fld[i]) || \ + tp##_is_any_nan(xb.fld[i]))) { \ + fe_flag = 1; \ + } else if ((e_b <= emin) || (e_b >= (emax-2))) { \ + fe_flag = 1; \ + } else if (!tp##_is_zero(xa.fld[i]) && \ + (((e_a - e_b) >= emax) || \ + ((e_a - e_b) <= (emin+1)) || \ + (e_a <= (emin+nbits)))) { \ + fe_flag = 1; \ + } \ + \ + if (unlikely(tp##_is_zero_or_denormal(xb.fld[i]))) { \ + fg_flag = 1; \ + } \ + } \ + } \ + \ + env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \ +} + +VSX_TDIV(xstdivdp, 1, float64, f64, -1022, 1023, 52) +VSX_TDIV(xvtdivdp, 2, float64, f64, -1022, 1023, 52) +VSX_TDIV(xvtdivsp, 4, float32, f32, -126, 127, 23) diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 02ea86c..316b16f 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -258,6 +258,7 @@ DEF_HELPER_2(xsdivdp, void, env, i32) DEF_HELPER_2(xsredp, void, env, i32) DEF_HELPER_2(xssqrtdp, void, env, i32) DEF_HELPER_2(xsrsqrtedp, void, env, i32) +DEF_HELPER_2(xstdivdp, void, env, i32) DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) @@ -266,6 +267,7 @@ DEF_HELPER_2(xvdivdp, void, env, i32) DEF_HELPER_2(xvredp, void, env, i32) DEF_HELPER_2(xvsqrtdp, void, env, i32) DEF_HELPER_2(xvrsqrtedp, void, env, i32) +DEF_HELPER_2(xvtdivdp, void, env, i32) DEF_HELPER_2(xvaddsp, void, env, i32) DEF_HELPER_2(xvsubsp, void, env, i32) @@ -274,6 +276,7 @@ DEF_HELPER_2(xvdivsp, void, env, i32) DEF_HELPER_2(xvresp, void, env, i32) DEF_HELPER_2(xvsqrtsp, void, env, i32) DEF_HELPER_2(xvrsqrtesp, void, env, i32) +DEF_HELPER_2(xvtdivsp, void, env, i32) DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index b5253fc..fe071f0 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7300,6 +7300,7 @@ GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX) GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) @@ -7308,6 +7309,7 @@ GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX) @@ -7316,6 +7318,7 @@ GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX) #define VSX_LOGICAL(name, tcg_op) \ static void glue(gen_, name)(DisasContext * ctx) \ @@ -10006,6 +10009,7 @@ GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX), GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX), GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX), GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX), +GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX), GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), @@ -10014,6 +10018,7 @@ GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX), GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX), GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX), GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX), +GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX), GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX), GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX), @@ -10022,6 +10027,7 @@ GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX), GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX), GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX), GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX), +GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX), #undef VSX_LOGICAL #define VSX_LOGICAL(name, opc2, opc3, fl2) \