From patchwork Thu Oct 3 14:34:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 280347 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9704E2C00AA for ; Fri, 4 Oct 2013 00:34:46 +1000 (EST) Received: from localhost ([::1]:43551 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VRjzG-0005s7-6l for incoming@patchwork.ozlabs.org; Thu, 03 Oct 2013 10:34:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VRjyr-0005s2-Sc for qemu-devel@nongnu.org; Thu, 03 Oct 2013 10:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VRjyl-0007ax-DL for qemu-devel@nongnu.org; Thu, 03 Oct 2013 10:34:17 -0400 Received: from mail-bk0-f49.google.com ([209.85.214.49]:33934) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VRjyl-0007aq-3G for qemu-devel@nongnu.org; Thu, 03 Oct 2013 10:34:11 -0400 Received: by mail-bk0-f49.google.com with SMTP id r7so965409bkg.36 for ; Thu, 03 Oct 2013 07:34:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:date:from:user-agent:mime-version:to :cc:subject:content-type:content-transfer-encoding; bh=T3FLNuXuErdw+z1qREb9X5nb4Zcy8eiPV6fDSezvZ8A=; b=Nn9AtxEhI1zLiL0cgvPCOlkjCdiTPM6Bh8QilQKOzQcZn5TKDZNc0Fln7Y+qoS6jQJ FHWxxWFRcj2IUftg2utLLfe58zwfm918JXFds+EsPXO88dWagcQZDbzOtNQviwJh9hLf KotLgMXdRaRrfc+zvxKsKvGYajJqe2sFju7lpbm7XZvEUg7V75JPhXr8qpF7JAvlKEkG u0Wbe3mJNCRxGweHgoaVKa8BvQaNQfQ2DTWvkWVp+6nHHXWcWPqw5brBT3xpgaDE2DQ9 b9vsbzvM50DuxERc6M1282pa6jY8Cu186/mnW0ozq5+XcdyfakHyEVc+ewW0lWhCClgV QE8w== X-Gm-Message-State: ALoCoQn4TsBrMtFy/IOryxaQFcyanwFaRPiU+0YomMhdk4vZSCNHoDmORWx566H49pGI/5ZFKE4r X-Received: by 10.204.228.10 with SMTP id jc10mr7946143bkb.26.1380810849725; Thu, 03 Oct 2013 07:34:09 -0700 (PDT) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginmedia.com. [82.1.113.198]) by mx.google.com with ESMTPSA id on10sm4940949bkb.13.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Oct 2013 07:34:08 -0700 (PDT) Message-ID: <524D805F.5080401@linaro.org> Date: Thu, 03 Oct 2013 15:34:07 +0100 From: Will Newton User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130805 Thunderbird/17.0.8 MIME-Version: 1.0 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.214.49 Cc: patches@linaro.org Subject: [Qemu-devel] [PATCH v3] target-arm: Implement ARMv8 VSEL instruction. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This adds support for the VSEL floating point selection instruction which was added in ARMv8. Signed-off-by: Will Newton --- target-arm/translate.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 110 insertions(+), 5 deletions(-) Changes in v3: - Move calls to disas_vfp_insn out of disas_coproc_insn diff --git a/target-arm/translate.c b/target-arm/translate.c index 998bde2..10b4fac 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2880,6 +2880,99 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) rm = VFP_SREG_M(insn); } + if ((insn & 0x0f800e50) == 0x0e000a00) { + /* vsel */ + uint32_t cc = (insn >> 20) & 3; + TCGv_i32 tmp, zero; + + /* ARMv8 VFP. */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + return 1; + } + + zero = tcg_const_tl(0); + + if (dp) { + TCGv_i64 ftmp1, ftmp2, ftmp3; + + ftmp1 = tcg_temp_new_i64(); + ftmp2 = tcg_temp_new_i64(); + ftmp3 = tcg_temp_new_i64(); + tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm)); + switch (cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, cpu_ZF, zero, + ftmp1, ftmp2); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, cpu_VF, zero, + ftmp1, ftmp2); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero, + ftmp1, ftmp2); + tcg_temp_free_i32(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, cpu_ZF, zero, + ftmp1, ftmp2); + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero, + ftmp3, ftmp2); + tcg_temp_free_i32(tmp); + break; + } + tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(ftmp1); + tcg_temp_free_i64(ftmp2); + tcg_temp_free_i64(ftmp3); + } else { + TCGv_i32 ftmp1, ftmp2, ftmp3; + + ftmp1 = tcg_temp_new_i32(); + ftmp2 = tcg_temp_new_i32(); + ftmp3 = tcg_temp_new_i32(); + tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm)); + switch (cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF, zero, + ftmp1, ftmp2); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF, zero, + ftmp1, ftmp2); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero, + ftmp1, ftmp2); + tcg_temp_free_i32(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF, zero, + ftmp1, ftmp2); + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero, + ftmp3, ftmp2); + tcg_temp_free_i32(tmp); + break; + } + tcg_gen_st_f32(ftmp3, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(ftmp1); + tcg_temp_free_i32(ftmp2); + tcg_temp_free_i32(ftmp3); + } + + return 0; + } + veclen = s->vec_len; if (op == 15 && rn > 3) veclen = 0; @@ -6299,9 +6392,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) return disas_dsp_insn(env, s, insn); } return 1; - case 10: - case 11: - return disas_vfp_insn (env, s, insn); default: break; } @@ -6756,6 +6846,11 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) goto illegal_op; return; } + if ((insn & 0x0f000e10) == 0x0e000a00) { + /* VFP. */ + if (disas_vfp_insn(env, s, insn)) + goto illegal_op; + } if (((insn & 0x0f30f000) == 0x0510f000) || ((insn & 0x0f30f010) == 0x0710f000)) { if ((insn & (1 << 22)) == 0) { @@ -8036,9 +8131,15 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) case 0xc: case 0xd: case 0xe: - /* Coprocessor. */ - if (disas_coproc_insn(env, s, insn)) + if (((insn >> 8) & 0xe) == 10) { + /* VFP. */ + if (disas_vfp_insn(env, s, insn)) { + goto illegal_op; + } + } else if (disas_coproc_insn(env, s, insn)) { + /* Coprocessor. */ goto illegal_op; + } break; case 0xf: /* swi */ @@ -8768,6 +8869,10 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); if (disas_neon_data_insn(env, s, insn)) goto illegal_op; + } else if (((insn >> 8) & 0xe) == 10) { + if (disas_vfp_insn(env, s, insn)) { + goto illegal_op; + } } else { if (insn & (1 << 28)) goto illegal_op;