From patchwork Fri Oct 9 13:28:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Davidsaver X-Patchwork-Id: 528370 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:4830:134:3::10]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C763F140E41 for ; Sat, 10 Oct 2015 05:04:55 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=NkPePdSl; dkim-atps=neutral Received: from lists.gnu.org ([208.118.235.17]:59765) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zkc2H-0008JW-CX for incoming@patchwork.ozlabs.org; Fri, 09 Oct 2015 14:04:53 -0400 Received: from localhost ([::1]:40345 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkbPv-0006VK-75 for incoming@patchwork.ozlabs.org; Fri, 09 Oct 2015 13:25:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38317) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkXjM-0003zw-Ci for qemu-devel@nongnu.org; Fri, 09 Oct 2015 09:29:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZkXjK-00057R-2J for qemu-devel@nongnu.org; Fri, 09 Oct 2015 09:29:04 -0400 Received: from mail-qg0-x22e.google.com ([2607:f8b0:400d:c04::22e]:36424) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZkXjJ-00057N-V9 for qemu-devel@nongnu.org; Fri, 09 Oct 2015 09:29:02 -0400 Received: by qgx61 with SMTP id 61so68301024qgx.3 for ; Fri, 09 Oct 2015 06:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MN9VXDrE7qvASZksUfes6dlauibizrMb7XTjSSxk0zk=; b=NkPePdSloc2YBkFeYWJYlMzZnZ+onGu3sb1fpRz5OS2XoSH52nIFf15MSGjhITYYTV hTQxqq1AtI7pzsHXrdKhPFaijaAkIAWBWEY4o72MA3DNfMXyEVCWMGQgKBKgre9YQuTc imgoBVvtJwcB0asZyPP7rVJQcao0JuVNijVnSVnpl09kVwyGZG2ahD/sF1vld9ArpcJN iK06KGB1sOdUxeemXXZNeM57L6CmI5rju0L8L3FyM2Nf72mXecrAZgDc6R8rR2pSbKA6 k8LqWnHlNT0ZSYwCMMCsXNuoJSxS16lS8U/aRCBBBBLrwoxNAEzHa9Q+NrmCEP7GTxI+ uxZA== X-Received: by 10.140.44.11 with SMTP id f11mr15029751qga.80.1444397341750; Fri, 09 Oct 2015 06:29:01 -0700 (PDT) Received: from desktop.local (ool-182df582.dyn.optonline.net. [24.45.245.130]) by smtp.gmail.com with ESMTPSA id z10sm623034qhd.15.2015.10.09.06.29.00 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Oct 2015 06:29:01 -0700 (PDT) From: Michael Davidsaver To: qemu-devel@nongnu.org Date: Fri, 9 Oct 2015 09:28:30 -0400 Message-Id: <4f38333687b11b590c8129995f8da735757e9629.1444396783.git.mdavidsaver@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400d:c04::22e Cc: Peter Crosthwaite , Michael Davidsaver Subject: [Qemu-devel] [PATCH 2/3] armv7-m: fix non-IRQ exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x Handlers will not be entered unless v7m.exception is updated. For example, an invalid instruction won't invoke UsageError, but rather re-executes the invalid instruction forever. Add warn and fix of mis-aligned handlers. Ensure exception return "addresses" always fault, and trap them just before the EXCP_DATA_ABORT handler would be invoked and execute return instead of MemManage. This removes the need for the "armv7m.hack" MemoryRegion. --- hw/arm/armv7m.c | 8 -------- target-arm/helper.c | 27 +++++++++++++++++++++------ 2 files changed, 21 insertions(+), 14 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index eb214db..0fc95de 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -178,7 +178,6 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, uint64_t lowaddr; int i; int big_endian; - MemoryRegion *hack = g_new(MemoryRegion, 1); if (cpu_model == NULL) { cpu_model = "cortex-m3"; @@ -226,13 +225,6 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, } } - /* Hack to map an additional page of ram at the top of the address - space. This stops qemu complaining about executing code outside RAM - when returning from an exception. */ - memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000, &error_fatal); - vmstate_register_ram_global(hack); - memory_region_add_subregion(system_memory, 0xfffff000, hack); - qemu_register_reset(armv7m_reset, cpu); return pic; } diff --git a/target-arm/helper.c b/target-arm/helper.c index 8367997..56b238f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5346,18 +5346,23 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - return; + env->v7m.exception = ARMV7M_EXCP_USAGE; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); - return; + env->v7m.exception = ARMV7M_EXCP_SVC; + break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - /* TODO: if we implemented the MPU registers, this is where we - * should set the MMFAR, etc from exception.fsr and exception.vaddress. - */ + if(env->v7m.exception!=0 && env->exception.vaddress>=0xfffffff0) { + /* this isn't a real fault, but rather a result of return from interrupt */ + do_v7m_exception_exit(env); + return; + } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); - return; + env->v7m.exception = ARMV7M_EXCP_MEM; + break; case EXCP_BKPT: if (semihosting_enabled()) { int nr; @@ -5407,6 +5412,12 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + if(!env->thumb) { + qemu_log_mask(LOG_GUEST_ERROR, + "M profile interrupt handler with misaligned " + "PC is UNPREDICTABLE\n"); + env->thumb = 1; + } } /* Function used to synchronize QEMU's AArch64 register set with AArch32 @@ -6682,6 +6693,10 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, *phys_ptr = address; *prot = 0; + /* ensure exception returns take precidence */ + if(env->v7m.exception!=0 && env->exception.vaddress>=0xfffffff0) + return true; + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* MPU enabled */