From patchwork Wed Mar 14 13:01:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Starikovskiy X-Patchwork-Id: 146642 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 80B19B6EF3 for ; Thu, 15 Mar 2012 02:48:04 +1100 (EST) Received: from localhost ([::1]:51364 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7oQR-000157-7Y for incoming@patchwork.ozlabs.org; Wed, 14 Mar 2012 09:39:35 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7npt-00080J-Mk for qemu-devel@nongnu.org; Wed, 14 Mar 2012 09:01:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7npR-0007zL-CV for qemu-devel@nongnu.org; Wed, 14 Mar 2012 09:01:49 -0400 Received: from mail-bk0-f45.google.com ([209.85.214.45]:59783) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7npQ-0007xt-WC for qemu-devel@nongnu.org; Wed, 14 Mar 2012 09:01:21 -0400 Received: by bkcjg9 with SMTP id jg9so1552171bkc.4 for ; Wed, 14 Mar 2012 06:01:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:subject:references :in-reply-to:content-type:content-transfer-encoding; bh=Vsq9/X5KWgg98cKI/1uf/jFUL3/Sd9yxfnT8jWVQJi0=; b=sfboIO+RdHntotmiCxe+5aBET37Odnf2GwYPa93Bw2KgdGnqfLDRMAO9RM0B8vlajy M9AMf47kBy1LFb/Skab8VqPr44tHzu09Ngly3YgHMDI9nrmib61pslXMaSKEpcXQLAdP WpVVyeddE1QE8ad9RT6PjYdK5q3e18xK9Uz6Ha8qtMD7djg6ZF+rhEXZnmgxA1+k3Ht5 vzDXQeIUleTfU6lvW8fGemwXX/IFBJtDWP40TH6RzZNSkFNMrxrtnIWzQkVuIB33eu+c QtaozzOQoWVnYngRBt+osrY3fIMRUOq61gF85kNiYTm5BbcitikdKOKJi6ObemaEoC2l MVgw== Received: by 10.204.156.18 with SMTP id u18mr938139bkw.32.1331730078867; Wed, 14 Mar 2012 06:01:18 -0700 (PDT) Received: from [10.30.10.79] ([80.251.228.149]) by mx.google.com with ESMTPS id f6sm7811303bkg.10.2012.03.14.06.01.18 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 14 Mar 2012 06:01:18 -0700 (PDT) Message-ID: <4F60969D.3040100@gmail.com> Date: Wed, 14 Mar 2012 17:01:17 +0400 From: Alexey Starikovskiy User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.27) Gecko/20120216 Thunderbird/3.1.19 MIME-Version: 1.0 To: qemu-devel@nongnu.org References: <4F609652.9070701@gmail.com> In-Reply-To: <4F609652.9070701@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.214.45 X-Mailman-Approved-At: Wed, 14 Mar 2012 09:37:51 -0400 Subject: [Qemu-devel] [PATCH v2 2/3] Support for MRCC and MCRR instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Alexey Starikovskiy --- target-arm/helper.c | 28 ++++++++++++++++++++++++++++ target-arm/helper.h | 2 ++ target-arm/translate.c | 47 +++++++++++++++++++++++++++++------------------ 3 files changed, 59 insertions(+), 18 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index d190104..3c4c0e4 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -670,6 +670,16 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) cpu_abort(env, "cp15 insn %08x\n", insn); } +void HELPER(set_cp15_64)(CPUState * env, uint32_t insn, uint64_t val) +{ + cpu_abort(env, "cp15 insn %08x\n", insn); +} + +uint64_t HELPER(get_cp15_64)(CPUState * env, uint32_t insn) +{ + cpu_abort(env, "cp15 insn %08x\n", insn); +} + /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val) { @@ -2261,6 +2271,24 @@ bad_reg: return 0; } +void HELPER(set_cp15_64)(CPUState *env, uint32_t insn, uint64_t val) +{ + int crm = insn& 0xf; + int opc1 = (insn>> 4)& 0xf; + cpu_abort(env, "Unimplemented cp15 register 64bit write (c%d[%d])\n", + crm, opc1); +} + +uint64_t HELPER(get_cp15_64)(CPUState *env, uint32_t insn) +{ + /* Used for block cache operations, so just return 0 */ +#if 0 + cpu_abort(env, "Unimplemented cp15 register 64bit read (c%d[%d])\n", + crm, opc1); +#endif + return 0; +} + void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val) { if ((env->uncached_cpsr& CPSR_M) == mode) { diff --git a/target-arm/helper.h b/target-arm/helper.h index 16dd5fc..bc8151c 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -60,7 +60,9 @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) DEF_HELPER_3(set_cp15, void, env, i32, i32) +DEF_HELPER_3(set_cp15_64, void, env, i32, i64) DEF_HELPER_2(get_cp15, i32, env, i32) +DEF_HELPER_2(get_cp15_64, i64, env, i32) DEF_HELPER_3(set_cp, void, env, i32, i32) DEF_HELPER_2(get_cp, i32, env, i32) diff --git a/target-arm/translate.c b/target-arm/translate.c index 280bfca..27ba5fb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2559,17 +2559,9 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) /* M profile cores use memory mapped registers instead of cp15. */ if (arm_feature(env, ARM_FEATURE_M)) - return 1; + return 1; - if ((insn& (1<< 25)) == 0) { - if (insn& (1<< 20)) { - /* mrrc */ - return 1; - } - /* mcrr. Used for block cache operations, so implement as no-op. */ - return 0; - } - if ((insn& (1<< 4)) == 0) { + if ((insn& (1<< 4)) == 0&& (insn& (1<< 25))) { /* cdp */ return 1; } @@ -2636,16 +2628,35 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) tmp2 = tcg_const_i32(insn); if (insn& ARM_CP_RW_BIT) { - tmp = tcg_temp_new_i32(); - gen_helper_get_cp15(tmp, cpu_env, tmp2); - /* If the destination register is r15 then sets condition codes. */ - if (rd != 15) - store_reg(s, rd, tmp); - else - tcg_temp_free_i32(tmp); + if ((insn& (1<< 25))) { + tmp = tcg_temp_new_i32(); + gen_helper_get_cp15(tmp, cpu_env, tmp2); + /* If the destination register is r15 then sets condition codes. */ + if (rd != 15) { + store_reg(s, rd, tmp); + } else { + tcg_temp_free_i32(tmp); + } + } else { + int rd1 = (insn>> 16)& 0xf; + TCGv_i64 tmp1 = tcg_temp_new_i64(); + gen_helper_get_cp15_64(tmp1, cpu_env, tmp2); + tcg_gen_trunc_i64_i32(cpu_R[rd], tmp1); + tcg_gen_shri_i64(tmp1, tmp1, 32); + tcg_gen_trunc_i64_i32(cpu_R[rd1], tmp1); + tcg_temp_free_i64(tmp1); + } } else { tmp = load_reg(s, rd); - gen_helper_set_cp15(cpu_env, tmp2, tmp); + if ((insn& (1<< 25))) { + gen_helper_set_cp15(cpu_env, tmp2, tmp); + } else { + int rd1 = (insn>> 16)& 0xf; + TCGv_i64 tmp1 = tcg_temp_new_i64(); + tcg_gen_concat_i32_i64(tmp1, cpu_R[rd], cpu_R[rd1]); + gen_helper_set_cp15_64(cpu_env, tmp2, tmp1); + tcg_temp_free_i64(tmp1); + } tcg_temp_free_i32(tmp); /* Normally we would always end the TB here, but Linux * arch/arm/mach-pxa/sleep.S expects two instructions following