From patchwork Tue Dec 20 19:13:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Langsdorf X-Patchwork-Id: 132508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 86838B7052 for ; Wed, 21 Dec 2011 06:14:02 +1100 (EST) Received: from localhost ([::1]:39513 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd58L-0008Mq-SL for incoming@patchwork.ozlabs.org; Tue, 20 Dec 2011 14:13:53 -0500 Received: from eggs.gnu.org ([140.186.70.92]:48719) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd58F-0008Mi-R6 for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:13:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rd58A-0006yA-SQ for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:13:47 -0500 Received: from smtp191.dfw.emailsrvr.com ([67.192.241.191]:59170) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rd58A-0006y6-Nc for qemu-devel@nongnu.org; Tue, 20 Dec 2011 14:13:42 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp19.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id 3C94F3C82F5; Tue, 20 Dec 2011 14:13:42 -0500 (EST) X-Virus-Scanned: OK Received: by smtp19.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id 156D63C86DD; Tue, 20 Dec 2011 14:13:42 -0500 (EST) Message-ID: <4EF0DE68.6030000@calxeda.com> Date: Tue, 20 Dec 2011 13:13:44 -0600 From: Mark Langsdorf User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 MIME-Version: 1.0 To: qemu-devel@nongnu.org, peter.maydell@linaro.org, paul@codesourcery.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 67.192.241.191 Subject: [Qemu-devel] [PATCH 7/9] add L2x0/PL310 cache controller device X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Rob Herring This is just a dummy device for ARM L2 cache controllers. Signed-off-by: Rob Herring Signed-off-by: Mark Langsdorf --- Makefile.target | 2 +- hw/arm_l2x0.c | 109 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+), 1 deletions(-) create mode 100644 hw/arm_l2x0.c +device_init(l2x0_register_device) + diff --git a/Makefile.target b/Makefile.target index 3261383..e4132d6 100644 --- a/Makefile.target +++ b/Makefile.target @@ -335,7 +335,7 @@ endif obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o obj-arm-y += arm_boot.o pl011.o pl031.o pl050.o pl080.o pl110.o pl181.o pl190.o obj-arm-y += versatile_pci.o -obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o +obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o arm_l2x0.o obj-arm-y += arm_mptimer.o obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o obj-arm-y += pl061.o diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c new file mode 100644 index 0000000..ce13311 --- /dev/null +++ b/hw/arm_l2x0.c @@ -0,0 +1,109 @@ +/* + * ARM dummy L210, L220, PL310 cache controller. + * + * Copyright (c) 2006-2007 CodeSourcery. + * Copyright (c) 2010-2012 Calxeda + * Written by Rob Herring + * + * This code is licenced under the GPL. + */ + +#include "sysbus.h" + +typedef struct l2x0_state { + SysBusDevice busdev; + MemoryRegion iomem; + uint32_t ctrl; + uint32_t aux_ctrl; + uint32_t data_ctrl; + uint32_t tag_ctrl; + uint32_t filter_start; + uint32_t filter_end; +} l2x0_state; + +static uint64_t l2x0_priv_read(void *opaque, target_phys_addr_t offset, unsigned size) +{ + l2x0_state *s = (l2x0_state *)opaque; + offset &= 0xfff; + if (offset == 0) + return 0x410000c6; + else if (offset == 0x4) + return 0x19080800; + else if (offset == 0x100) + return s->ctrl; + else if (offset == 0x104) + return s->aux_ctrl; + else if (offset == 0x108) + return s->tag_ctrl; + else if (offset == 0x10C) + return s->data_ctrl; + else if (offset >= 0x730 && offset < 0x800) + return 0; /* cache ops complete */ + else if (offset == 0xC00) + return s->filter_start; + else if (offset == 0xC04) + return s->filter_end; + else if (offset == 0xF40) + return 0; + else if (offset == 0xF60) + return 0; + else if (offset == 0xF80) + return 0; + + hw_error("l2x0_priv_read: Bad offset %x\n", (int)offset); + return 0; +} + +static void l2x0_priv_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) +{ + l2x0_state *s = (l2x0_state *)opaque; + offset &= 0xfff; + if (offset == 0x100) + s->ctrl = value & 1; + else if (offset == 0x104) + s->aux_ctrl = value; + else if (offset == 0x108) + s->tag_ctrl = value; + else if (offset == 0x10C) + s->data_ctrl = value; + else if (offset >= 0x730 && offset < 0x800) + /* ignore */ + return; + else if (offset == 0xC00) + s->filter_start = value; + else if (offset == 0xC04) + s->filter_end = value; + else if (offset == 0xF40) + return; + else if (offset == 0xF60) + return; + else if (offset == 0xF80) + return; + else + hw_error("l2x0_priv_write: Bad offset %x\n", (int)offset); +} + +static const MemoryRegionOps l2x0_mem_ops = { + .read = l2x0_priv_read, + .write = l2x0_priv_write, + .endianness = DEVICE_NATIVE_ENDIAN, + }; + +static int l2x0_priv_init(SysBusDevice *dev) +{ + l2x0_state *s = FROM_SYSBUS(l2x0_state, dev); + + s->aux_ctrl = 0x00020000; + + memory_region_init_io(&s->iomem, &l2x0_mem_ops, s, "l2x0_cc", 0x1000); + sysbus_init_mmio(dev, &s->iomem); + return 0; +} + +static void l2x0_register_device(void) +{ + sysbus_register_dev("l2x0_cc", sizeof(l2x0_state), l2x0_priv_init); +} +