From patchwork Fri Dec 16 18:58:54 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Huber X-Patchwork-Id: 131892 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AA35D1007DB for ; Sat, 17 Dec 2011 06:29:33 +1100 (EST) Received: from localhost ([::1]:43764 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RbdTF-0004OZ-Bo for incoming@patchwork.ozlabs.org; Fri, 16 Dec 2011 14:29:29 -0500 Received: from eggs.gnu.org ([140.186.70.92]:37312) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RbdT8-0004OJ-U6 for qemu-devel@nongnu.org; Fri, 16 Dec 2011 14:29:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RbdT7-0006DN-UH for qemu-devel@nongnu.org; Fri, 16 Dec 2011 14:29:22 -0500 Received: from host-82-135-62-35.customer.m-online.net ([82.135.62.35]:52581 helo=mail.embedded-brains.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RbdT7-0006DG-Gm for qemu-devel@nongnu.org; Fri, 16 Dec 2011 14:29:21 -0500 Received: by mail.embedded-brains.de (Postfix, from userid 65534) id 2DDB06526B6; Fri, 16 Dec 2011 19:51:11 +0100 (CET) Received: from linux-an7x.site (38.vpnclient.eb.z [192.168.126.38]) by mail.embedded-brains.de (Postfix) with ESMTP id B83116526B4 for ; Fri, 16 Dec 2011 19:51:07 +0100 (CET) Message-ID: <4EEB94EE.1010808@embedded-brains.de> Date: Fri, 16 Dec 2011 19:58:54 +0100 From: Sebastian Huber User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-GB; rv:1.9.2.23) Gecko/20110920 SUSE/3.1.15 Thunderbird/3.1.15 MIME-Version: 1.0 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 82.135.62.35 Subject: [Qemu-devel] [PATCH] target-arm: Fixed ARMv7-M SHPR access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Hello, this may help to fix Bug 696094. From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 16 Dec 2011 19:46:40 +0100 Subject: [PATCH] target-arm: Fixed ARMv7-M SHPR access According to "ARMv7-M Architecture Reference Manual" issue D section "B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy Register 3, SHPR3". Signed-off-by: Sebastian Huber --- hw/arm_gic.c | 16 ++++++++++++++-- hw/armv7m_nvic.c | 19 ------------------- 2 files changed, 14 insertions(+), 21 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 9b52119..5139d95 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) if (GIC_TEST_TRIGGER(irq + i)) res |= (2 << (i * 2)); } +#else + } else if (0xd18 <= offset && offset < 0xd24) { + /* System Handler Priority. */ + irq = offset - 0xd14; + res = GIC_GET_PRIORITY(irq, cpu); #endif } else if (offset < 0xfe0) { goto bad_reg; @@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) gic_state *s = (gic_state *)opaque; uint32_t addr; addr = offset; - if (addr < 0x100 || addr > 0xd00) + if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c + && addr != 0xd20)) return nvic_readl(s, addr); #endif val = gic_dist_readw(opaque, offset); @@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, GIC_CLEAR_TRIGGER(irq + i); } } +#else + } else if (0xd18 <= offset && offset < 0xd24) { + /* System Handler Priority. */ + irq = offset - 0xd14; + s->priority1[irq][0] = value & 0xff; #endif } else { /* 0xf00 is only handled for 32-bit writes. */ @@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset, #ifdef NVIC uint32_t addr; addr = offset; - if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) { + if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c + && addr != 0xd20 && addr != 0xf00)) { nvic_writel(s, addr, value); return; } diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index bf8c3c5..65b575e 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) case 0xd14: /* Configuration Control. */ /* TODO: Implement Configuration Control bits. */ return 0; - case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ - irq = offset - 0xd14; - val = 0; - val |= s->gic.priority1[irq++][0]; - val |= s->gic.priority1[irq++][0] << 8; - val |= s->gic.priority1[irq++][0] << 16; - val |= s->gic.priority1[irq][0] << 24; - return val; case 0xd24: /* System Handler Status. */ val = 0; if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); @@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) case 0xd14: /* Configuration Control. */ /* TODO: Implement control registers. */ goto bad_reg; - case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ - { - int irq; - irq = offset - 0xd14; - s->gic.priority1[irq++][0] = value & 0xff; - s->gic.priority1[irq++][0] = (value >> 8) & 0xff; - s->gic.priority1[irq++][0] = (value >> 16) & 0xff; - s->gic.priority1[irq][0] = (value >> 24) & 0xff; - gic_update(&s->gic); - } - break; case 0xd24: /* System Handler Control. */ /* TODO: Real hardware allows you to set/clear the active bits under some circumstances. We don't implement this. */ -- 1.7.1