| Message ID | 453290537c0f31507ea5e44ac824f45427b9ac1e.1529398335.git.balaton@eik.bme.hu |
|---|---|
| State | New |
| Headers | show |
| Series | Misc sam460ex improvements | expand |
On Tue, Jun 19, 2018 at 10:52:15AM +0200, BALATON Zoltan wrote: > According to PPC440 User Manual PPC440 has multiple opcodes for icbt > instruction: one for compatibility with older cores and two 440 > specific opcodes one of which is defined in BookE. QEMU only > implements two of these, add the missing one. > > Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Applied to ppc-for-3.0, thanks. > --- > v4: Updated commit message, for reference see bottom of: > http://manualzilla.com/doc/6915682/ppc440-processor-user-s-manual?page=451 > > target/ppc/translate.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 5fe1ba6..3a215a1 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6707,6 +6707,8 @@ GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, > GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), > GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, > PPC_BOOKE, PPC2_BOOKE206), > +GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, > + PPC_440_SPEC), > GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), > GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), > GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5fe1ba6..3a215a1 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6707,6 +6707,8 @@ GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER2(icbt_440, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, + PPC_440_SPEC), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
According to PPC440 User Manual PPC440 has multiple opcodes for icbt instruction: one for compatibility with older cores and two 440 specific opcodes one of which is defined in BookE. QEMU only implements two of these, add the missing one. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> --- v4: Updated commit message, for reference see bottom of: http://manualzilla.com/doc/6915682/ppc440-processor-user-s-manual?page=451 target/ppc/translate.c | 2 ++ 1 file changed, 2 insertions(+)