From patchwork Thu Feb 11 22:20:54 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 45170 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7B49AB7CF2 for ; Fri, 12 Feb 2010 12:47:37 +1100 (EST) Received: from localhost ([127.0.0.1]:45621 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nfkck-0001ex-OE for incoming@patchwork.ozlabs.org; Thu, 11 Feb 2010 20:47:14 -0500 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NfkbE-0001Vk-MD for qemu-devel@nongnu.org; Thu, 11 Feb 2010 20:45:40 -0500 Received: from [199.232.76.173] (port=58964 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NfkbE-0001VP-7p for qemu-devel@nongnu.org; Thu, 11 Feb 2010 20:45:40 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NfkbB-0002jI-RW for qemu-devel@nongnu.org; Thu, 11 Feb 2010 20:45:40 -0500 Received: from mx20.gnu.org ([199.232.41.8]:52911) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Nfkb8-0002jA-Ty for qemu-devel@nongnu.org; Thu, 11 Feb 2010 20:45:37 -0500 Received: from are.twiddle.net ([75.149.56.221]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NfjqL-0001Yj-FR for qemu-devel@nongnu.org; Thu, 11 Feb 2010 19:57:13 -0500 Received: by are.twiddle.net (Postfix, from userid 5000) id 10040C29; Thu, 11 Feb 2010 16:54:14 -0800 (PST) Message-Id: <4375b210e2ec2400c7bd1294d85d1099bcc1385d.1265933757.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Thu, 11 Feb 2010 14:20:54 -0800 To: qemu-devel@nongnu.org X-detected-operating-system: by mx20.gnu.org: GNU/Linux 2.6 (newer, 2) X-detected-operating-system: by monty-python.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Subject: [Qemu-devel] [PATCH 1/6] Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. --- exec.c | 17 ----------------- target-alpha/cpu.h | 4 +++- target-arm/cpu.h | 3 +++ target-cris/cpu.h | 3 +++ target-i386/cpu.h | 11 +++++++++++ target-m68k/cpu.h | 3 +++ target-microblaze/cpu.h | 3 +++ target-mips/mips-defs.h | 4 ++++ target-ppc/cpu.h | 17 +++++++++++++++++ target-s390x/cpu.h | 5 +++++ target-sh4/cpu.h | 3 +++ target-sparc/cpu.h | 8 ++++++++ 12 files changed, 63 insertions(+), 18 deletions(-) diff --git a/exec.c b/exec.c index 8389c54..766568b 100644 --- a/exec.c +++ b/exec.c @@ -62,23 +62,6 @@ #define SMC_BITMAP_USE_THRESHOLD 10 -#if defined(TARGET_SPARC64) -#define TARGET_PHYS_ADDR_SPACE_BITS 41 -#elif defined(TARGET_SPARC) -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#elif defined(TARGET_ALPHA) -#define TARGET_PHYS_ADDR_SPACE_BITS 42 -#define TARGET_VIRT_ADDR_SPACE_BITS 42 -#elif defined(TARGET_PPC64) -#define TARGET_PHYS_ADDR_SPACE_BITS 42 -#elif defined(TARGET_X86_64) -#define TARGET_PHYS_ADDR_SPACE_BITS 42 -#elif defined(TARGET_I386) -#define TARGET_PHYS_ADDR_SPACE_BITS 36 -#else -#define TARGET_PHYS_ADDR_SPACE_BITS 32 -#endif - static TranslationBlock *tbs; int code_gen_max_blocks; TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index c0dff4b..c144b4b 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -41,7 +41,9 @@ #define TARGET_PAGE_BITS 13 -#define VA_BITS 43 +/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 44 +#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) /* Alpha major type */ enum { diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4a1c53f..3892db4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -405,6 +405,9 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, #define TARGET_PAGE_BITS 10 #endif +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #define cpu_init cpu_arm_init #define cpu_exec cpu_arm_exec #define cpu_gen_code cpu_arm_gen_code diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 0626cd8..26171ca 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -195,6 +195,9 @@ enum { #define TARGET_PAGE_BITS 13 #define MMAP_SHIFT TARGET_PAGE_BITS +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #define cpu_init cpu_cris_init #define cpu_exec cpu_cris_exec #define cpu_gen_code cpu_cris_gen_code diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 216b00e..7fb84db 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -872,6 +872,17 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_PAGE_BITS 12 +#ifdef TARGET_X86_64 +#define TARGET_PHYS_ADDR_SPACE_BITS 52 +/* ??? This is really 48 bits, sign-extended, but the only thing + accessible to userland with bit 48 set is the VSYSCALL, and that + is handled via other mechanisms. */ +#define TARGET_VIRT_ADDR_SPACE_BITS 47 +#else +#define TARGET_PHYS_ADDR_SPACE_BITS 36 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#endif + #define cpu_init cpu_x86_init #define cpu_exec cpu_x86_exec #define cpu_gen_code cpu_x86_gen_code diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 68a7e41..b2f37ec 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -210,6 +210,9 @@ void register_m68k_insns (CPUM68KState *env); #define TARGET_PAGE_BITS 10 #endif +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #define cpu_init cpu_m68k_init #define cpu_exec cpu_m68k_exec #define cpu_gen_code cpu_m68k_gen_code diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 1bf4875..5999386 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -253,6 +253,9 @@ enum { #define TARGET_PAGE_BITS 12 #define MMAP_SHIFT TARGET_PAGE_BITS +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #define cpu_init cpu_mb_init #define cpu_exec cpu_mb_exec #define cpu_gen_code cpu_mb_gen_code diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 54e80f1..0f6a956 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -8,6 +8,10 @@ #define TARGET_PAGE_BITS 12 #define MIPS_TLB_MAX 128 +/* ??? MIPS64 no doubt has a larger address space. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #if defined(TARGET_MIPS64) #define TARGET_LONG_BITS 64 #else diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index d15bba1..c91f8fe 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -29,6 +29,20 @@ #define TARGET_LONG_BITS 64 #define TARGET_PAGE_BITS 12 +/* Note that the official physical address space bits is 62-M where M + is implementation dependent. I've not looked up M for the set of + cpus we emulate at the system level. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 62 + +/* Note that the PPC environment architecture talks about 80 bit virtual + addresses, with segmentation. Obviously that's not all visible to a + single process, which is all we're concerned with here. */ +#ifdef TARGET_ABI32 +# define TARGET_VIRT_ADDR_SPACE_BITS 32 +#else +# define TARGET_VIRT_ADDR_SPACE_BITS 64 +#endif + #else /* defined (TARGET_PPC64) */ /* PowerPC 32 definitions */ #define TARGET_LONG_BITS 32 @@ -50,6 +64,9 @@ #define TARGET_PAGE_BITS 12 #endif /* defined(TARGET_PPCEMB) */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #endif /* defined (TARGET_PPC64) */ #define CPUState struct CPUPPCState diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 0e75e1c..56fc083 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -100,6 +100,11 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw #define TARGET_PAGE_BITS 12 +/* ??? This is certainly wrong for 64-bit s390x, but given that only KVM + emulation actually works, this is good enough for a placeholder. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #ifndef CONFIG_USER_ONLY extern int s390_virtio_hypercall(CPUState *env); extern void kvm_s390_virtio_irq(CPUState *env, int config_change, uint64_t token); diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 85f221d..18a5532 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -44,6 +44,9 @@ #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + #define SR_MD (1 << 30) #define SR_RB (1 << 29) #define SR_BL (1 << 28) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 5980deb..a9d61f6 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -7,10 +7,18 @@ #define TARGET_LONG_BITS 32 #define TARGET_FPREGS 32 #define TARGET_PAGE_BITS 12 /* 4k */ + +#define TARGET_PHYS_ADDR_SPACE_BITS 41 + +/* ??? This is a guess based on PAGE_OFFSET in the Linux kernel. */ +#define TARGET_VIRT_ADDR_SPACE_BITS 41 + #else #define TARGET_LONG_BITS 64 #define TARGET_FPREGS 64 #define TARGET_PAGE_BITS 13 /* 8k */ +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #define CPUState struct CPUSPARCState