From patchwork Mon Oct 26 15:27:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 536070 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 0018B140D7C for ; Tue, 27 Oct 2015 02:28:27 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=fSZb/PHz; dkim-atps=neutral Received: from localhost ([::1]:53498 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqjhB-0007Um-GE for incoming@patchwork.ozlabs.org; Mon, 26 Oct 2015 11:28:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58871) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqjgW-0006Nw-Lr for qemu-devel@nongnu.org; Mon, 26 Oct 2015 11:27:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZqjgV-00015y-QA for qemu-devel@nongnu.org; Mon, 26 Oct 2015 11:27:44 -0400 Received: from mail-pa0-x230.google.com ([2607:f8b0:400e:c03::230]:36514) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZqjgV-00015m-Kq for qemu-devel@nongnu.org; Mon, 26 Oct 2015 11:27:43 -0400 Received: by pacfv9 with SMTP id fv9so200120122pac.3 for ; Mon, 26 Oct 2015 08:27:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=GIiloDhYUK6L/1RmtFnq41JpYhhaQFNpHSzv4pWLz+k=; b=fSZb/PHz+0Fehlx1WxzwV89RTjuK6KSKek4hCBpjdhJehcd7BvGpEIJ0WSNmU29qVH vD7x5v+rEmayglCwkGJ8+hqB5PBkx/+WKIOEbTJEzMUlXCd3A0vIsrHUMrwSf3WHEBw2 1lw1zYQVDiTeJfflS+Vcr0c0Xt1FCaG32hA3SgoR23gB8IJAjB3lzmbIFsdplOLB4vjz OlP1nGZoSy2uIG3spjoiqFccteXhz4iSKWyygbvN7DLzyLdwyKPRbhKLK5fy0ofZqgzr XW0eLt5YBTxJazOR3B+CfLj5W0gHqdma7mrqO9w5h1VR+sMDAdZmcJBxyhdMHY04S3WY N1dA== X-Received: by 10.68.137.234 with SMTP id ql10mr22691864pbb.33.1445873263356; Mon, 26 Oct 2015 08:27:43 -0700 (PDT) Received: from pcrost-box.hsd1.ca.comcast.net (c-24-130-130-137.hsd1.ca.comcast.net. [24.130.130.137]) by smtp.gmail.com with ESMTPSA id rc5sm34569220pbc.95.2015.10.26.08.27.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Oct 2015 08:27:42 -0700 (PDT) From: Peter Crosthwaite X-Google-Original-From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Mon, 26 Oct 2015 08:27:25 -0700 Message-Id: <3b45270a4854d8868dc649bd41c72cfcb3dffd7b.1445842804.git.crosthwaite.peter@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::230 Cc: Peter Maydell , pbonzini@redhat.com, Peter Crosthwaite Subject: [Qemu-devel] [PATCH v1 3/6] arm: cpu: static inline cpu_arm_init() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Move this implementation up to the header so it is visible from system level code once the architecture is converted to arch-obj-y. Alternative would be to create init.c in target-arm/hw but this implementation is trivial enough for static inline. Cc: Peter Maydell Signed-off-by: Peter Crosthwaite --- target-arm/cpu.h | 6 +++++- target-arm/helper.c | 5 ----- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 4b702df..6b6485b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -509,7 +509,11 @@ typedef struct CPUARMState { #include "cpu-qom.h" -ARMCPU *cpu_arm_init(const char *cpu_model); +static inline ARMCPU *cpu_arm_init(const char *cpu_model) +{ + return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); +} + target_ulong do_arm_semihosting(CPUARMState *env); void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); diff --git a/target-arm/helper.c b/target-arm/helper.c index e7fda37..3118267 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4501,11 +4501,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } -ARMCPU *cpu_arm_init(const char *cpu_model) -{ - return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model)); -} - void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) { CPUState *cs = CPU(cpu);