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[104.10.248.117]) by smtp.gmail.com with ESMTPSA id de4sm5109021pbb.60.2015.10.09.20.13.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 09 Oct 2015 20:13:38 -0700 (PDT) From: Peter Crosthwaite X-Google-Original-From: Peter Crosthwaite To: qemu-devel@nongnu.org Date: Fri, 9 Oct 2015 20:13:27 -0700 Message-Id: <39b6ef7741d456248c920b0b2b5f5219d139166b.1443931379.git.crosthwaite.peter@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::232 Cc: peter.maydell@linaro.org, Peter Crosthwaite , linux@roeck-us.net, robh@kernel.org Subject: [Qemu-devel] [RFC 3/3] arm: xilinx_zynq: Add linux pre-boot X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a Linux-specific pre-boot routine that matches the device specific bootloaders behaviour. This is needed for modern Linux that expects the ARM PLL in SLCR to be a more even value (not 26). FIXME: The blob population should only happen on Linux boots. Signed-off-by: Peter Crosthwaite --- hw/arm/xilinx_zynq.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 9f89483..5bf03de 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -43,6 +43,41 @@ static const int dma_irqs[8] = { 46, 47, 48, 49, 72, 73, 74, 75 }; +#define LOAD_ADDR 0x1000 +#define FW_BLOB_ADDR 0x0 + +#define SLCR_ARM_PLL_OFFSET 0x100 +#define SLCR_LOCK_OFFSET 0x004 +#define SLCR_UNLOCK_OFFSET 0x008 + +#define SLCR_XILINX_UNLOCK_KEY 0xdf0d +#define SLCR_XILINX_LOCK_KEY 0x767b + +#define SLCR_WRITE(addr, val) \ + 0xe3a01000 + extract32((val), 0, 8), \ + 0xe3811c00 + extract32((val), 8, 8), \ + 0xe3811800 + extract32((val), 16, 8), \ + 0xe3811400 + extract32((val), 24, 8), \ + 0xe5801000 + (addr), + +static void zynq_write_fw_blob(void) +{ + int n; + uint32_t fw_blob[] = { + 0xe3a004f8, /* mov r0, #0xf8000000 */ + SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY) + SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008) + //SLCR_WRITE(0x120, 0x1f000200) + SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY) + 0xe12fff1e, /* bx lr */ + }; + for (n = 0; n < ARRAY_SIZE(fw_blob); n++) { + fw_blob[n] = tswap32(fw_blob[n]); + } + rom_add_blob_fixed("firmware", fw_blob, sizeof(fw_blob), FW_BLOB_ADDR); +} + + static struct arm_boot_info zynq_binfo = {}; static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) @@ -251,7 +286,11 @@ static void zynq_init(MachineState *machine) zynq_binfo.initrd_filename = initrd_filename; zynq_binfo.nb_cpus = 1; zynq_binfo.board_id = 0xd32; - zynq_binfo.loader_start = 0; + zynq_binfo.loader_start = LOAD_ADDR; + zynq_binfo.board_setup_blob = true; + zynq_binfo.board_setup_blob_addr = FW_BLOB_ADDR; + + zynq_write_fw_blob(); arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo); }