[v2,24/35] target/riscv: Remove the hret instruction

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v2 24/35] target/riscv: Remove the hret instruction
Date: Fri, 31 Jan 2020 17:02:38 -0800
Message-Id: <39083deec532135287402aab20ab370f4cad68e3.1580518859.git.alistair.francis@wdc.com>
In-Reply-To: <cover.1580518859.git.alistair.francis@wdc.com>
References: <cover.1580518859.git.alistair.francis@wdc.com>
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Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com
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Message ID	39083deec532135287402aab20ab370f4cad68e3.1580518859.git.alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> IronPort-SDR: a/S5ajjofxy+CZ8PZt1cm6SB6I4hXmRPszn3JRGS+iWba8JgzDGa+hS3cSI/RFG8gUcSt/9Fhm iHIusxzdB2h2WbfGT/56MNaprhofd7WF+fKpu8T4gv2FLOusjjXMeTR9G7IZBs5gj7cugDdx3Z 41qjpIGdYAOD+QumHQ//86bzN4vl/JexGamHEuAXYBalu4NcAd2aFZ5Hl0L5HVdwLB2U+sEy9y 6ynfDhDaDlo7uGKXt9hIS2ulMBYPyx2nY9P4u3GZ2lhLf8CHWvOZLHdXg2BQGffZRPfoJCxwT5 lMU= IronPort-SDR: 78vd74HWmLlC8o1jerZJhtFBYA2TOA3POhLV3bm4Jr5rnzx+RjRUIxMXMagbPhtOSvoi6SHQ5L 9aB1ckefT/sl3qBGwtbVy5zDByodJZWKBzWR60zNxJh49AJyfLgCd0+ALbq2pntQr2sHa/+IQe DRYJzTS20ZO0nXm7mmeUuOut5ZXnQLU4QtT1h5HiN0GQLp8uYHCiDxYBh+3UJozH6qe9b/hnUE HbFgdn0yyYfAFdkYM6tVLi7gXIv7g42C3A5D23TLzZ44TdBDp0HYUuYuWXwrNoizjtNqbLebjA N1LHB9d6dL0ZcMCAKLfF90wG IronPort-SDR: rUmK1oE+zeiXw6gyVE7UZwWLDTywwi7lC0pm07A78awcq5d+9K8Rykx7uqvY6nKrVwUffzQFU0 /qLMC+TC6skaAD7+46TJVNsXnqC6Y+pDKk4NgRAI9Hw3CZuFOV7AHT3ovdx02+GrPUWyy7VfJq 3AnVu7X4PnLJOlQnWhvOF0S9beHII39Py/HVyiwQahqUNQYURa6FOloMzbQCn5U7ZHft5ZCUPM JZx5rDZ54kmd1SegkL/W2taAfEgmuGosecU2Oydr8+PuX9jYSQdD3iLtZoRlN0VgyAsMcmqT/W VP0= WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 24/35] target/riscv: Remove the hret instruction Date: Fri, 31 Jan 2020 17:02:38 -0800 Message-Id: <39083deec532135287402aab20ab370f4cad68e3.1580518859.git.alistair.francis@wdc.com> In-Reply-To: <cover.1580518859.git.alistair.francis@wdc.com> References: <cover.1580518859.git.alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	Add RISC-V Hypervisor Extension v0.5 \| expand [v2,00/35] Add RISC-V Hypervisor Extension v0.5 [v2,01/35] target/riscv: Convert MIP CSR to target_ulong [v2,02/35] target/riscv: Add the Hypervisor extension [v2,03/35] target/riscv: Add the Hypervisor CSRs to CPUState [v2,04/35] target/riscv: Add support for the new execption numbers [v2,05/35] target/riscv: Rename the H irqs to VS irqs [v2,06/35] target/riscv: Add the virtulisation mode [v2,07/35] target/riscv: Add the force HS exception mode [v2,08/35] target/riscv: Fix CSR perm checking for HS mode [v2,09/35] target/riscv: Print priv and virt in disas log [v2,10/35] target/riscv: Dump Hypervisor registers if enabled [v2,11/35] target/riscv: Add Hypervisor CSR access functions [v2,12/35] target/riscv: Add Hypervisor virtual CSRs accesses [v2,13/35] target/riscv: Add Hypervisor machine CSRs accesses [v2,14/35] target/riscv: Add virtual register swapping function [v2,15/35] target/riscv: Set VS bits in mideleg for Hyp extension [v2,16/35] target/riscv: Extend the MIE CSR to support virtulisation [v2,17/35] target/riscv: Extend the SIP CSR to support virtulisation [v2,18/35] target/riscv: Add support for virtual interrupt setting [v2,19/35] target/ricsv: Flush the TLB on virtulisation mode changes [v2,20/35] target/riscv: Generate illegal instruction on WFI when V=1 [v2,21/35] target/riscv: Add hypvervisor trap support [v2,22/35] target/riscv: Add Hypervisor trap return support [v2,23/35] target/riscv: Add hfence instructions [v2,24/35] target/riscv: Remove the hret instruction [v2,25/35] target/riscv: Only set TB flags with FP status if enabled [v2,26/35] target/riscv: Disable guest FP support based on virtual status [v2,27/35] target/riscv: Mark both sstatus and msstatus_hs as dirty [v2,28/35] target/riscv: Respect MPRV and SPRV for floating point ops [v2,29/35] target/riscv: Allow specifying MMU stage [v2,30/35] target/riscv: Implement second stage MMU [v2,31/35] target/riscv: Raise the new execptions when 2nd stage translation fails [v2,32/35] target/riscv: Set htval and mtval2 on execptions [v2,33/35] target/riscv: Add support for the 32-bit MSTATUSH CSR [v2,34/35] target/riscv: Add the MSTATUS_MPV_ISSET helper macro [v2,35/35] target/riscv: Allow enabling the Hypervisor extension

[v2,24/35] target/riscv: Remove the hret instruction

Commit Message

Patch