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[v5,4/8] target/mips: Add function to signal RI exception unless user only

Message ID 3645d754c001aa9ae3f4f363bf5d53f1fa1b2044.1537379317.git.noring@nocrew.org
State New
Headers show
Series target/mips: Support R5900 GCC programs in user mode | expand

Commit Message

Fredrik Noring Sept. 16, 2018, 3:04 p.m. UTC 
The Linux kernel traps and emulates certain instructions. For user only,
QEMU is the kernel, so we emulate those traps by simply emulating the
instructions directly.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c35be0053b..2fe46f8775 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1887,6 +1887,18 @@  static inline void check_insn_opc_removed(DisasContext *ctx, int flags)
     }
 }
 
+/*
+ * Unless user only, when the kernel emulates the code, a "reserved
+ * instruction" exception is generated if the CPU has corresponding
+ * flag set which indicates that the instruction has been removed.
+ */
+static inline void check_insn_opc_user_only(DisasContext *ctx, int flags)
+{
+#ifndef CONFIG_USER_ONLY
+    check_insn_opc_removed(ctx, flags);
+#endif
+}
+
 /* This code generates a "reserved instruction" exception if the
    CPU does not support 64-bit paired-single (PS) floating point data type */
 static inline void check_ps(DisasContext *ctx)