From patchwork Tue Apr 13 23:44:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 50184 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C20E3B7D40 for ; Thu, 15 Apr 2010 07:10:29 +1000 (EST) Received: from localhost ([127.0.0.1]:41195 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O29qr-0000uv-RG for incoming@patchwork.ozlabs.org; Wed, 14 Apr 2010 17:10:25 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O29XQ-0004lR-Cs for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:21 -0400 Received: from [140.186.70.92] (port=35396 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O29XE-0004XV-Km for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O29XD-0001P3-E6 for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:08 -0400 Received: from are.twiddle.net ([75.149.56.221]:41945) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O29XD-0001Oj-3F for qemu-devel@nongnu.org; Wed, 14 Apr 2010 16:50:07 -0400 Received: by are.twiddle.net (Postfix, from userid 5000) id 8164AEC5; Wed, 14 Apr 2010 13:50:06 -0700 (PDT) Message-Id: <34b3e2152f8d37d5de1b0f4f02cb0000c3fc9b7f.1271277329.git.rth@twiddle.net> In-Reply-To: References: From: Richard Henderson Date: Tue, 13 Apr 2010 16:44:35 -0700 To: qemu-devel@nongnu.org X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 06/21] tcg-i386: Tidy shift operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Define OPC_SHIFT_{1,Ib,cl}. Factor opcode emission to a function. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 47 +++++++++++++++++++++++------------------------ 1 files changed, 23 insertions(+), 24 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 0bafd00..2df45bf 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -168,6 +168,9 @@ static inline int tcg_target_const_match(tcg_target_long val, #define OPC_MOVZWL (0xb7 | P_EXT) #define OPC_MOVSBL (0xbe | P_EXT) #define OPC_MOVSWL (0xbf | P_EXT) +#define OPC_SHIFT_1 (0xd1) +#define OPC_SHIFT_Ib (0xc1) +#define OPC_SHIFT_cl (0xd3) #define ARITH_ADD 0 #define ARITH_OR 1 @@ -294,6 +297,16 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); } +static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count) +{ + if (count == 1) { + tcg_out_modrm(s, OPC_SHIFT_1, subopc, reg); + } else { + tcg_out_modrm(s, OPC_SHIFT_Ib, subopc, reg); + tcg_out8(s, count); + } +} + static void tcg_out_ext8u(TCGContext *s, int dest, int src) { if (src >= 4) { @@ -314,12 +327,8 @@ static void tcg_out_ext8s(TCGContext *s, int dest, int src) if (src >= 4) { tcg_out_mov(s, dest, src); if (dest >= 4) { - /* shl $24, dest */ - tcg_out_modrm(s, 0xc1, SHIFT_SHL, dest); - tcg_out8(s, 24); - /* sar $24, dest */ - tcg_out_modrm(s, 0xc1, SHIFT_SAR, dest); - tcg_out8(s, 24); + tcg_out_shifti(s, SHIFT_SHL, dest, 24); + tcg_out_shifti(s, SHIFT_SAR, dest, 24); return; } src = dest; @@ -351,9 +360,7 @@ static inline void tcg_out_bswap16(TCGContext *s, int reg, int sign) the sign or zero extension required. It also doesn't suffer the problem of partial register stalls that using rolw does. */ tcg_out_bswap32(s, reg); - /* shr $16, dest */ - tcg_out_modrm(s, 0xc1, (sign ? SHIFT_SAR : SHIFT_SHR), reg); - tcg_out8(s, 16); + tcg_out_shifti(s, (sign ? SHIFT_SAR : SHIFT_SHR), reg, 16); } static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val, int cf) @@ -648,9 +655,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, tcg_out_mov(s, r0, addr_reg); - tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */ - tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - + tcg_out_shifti(s, SHIFT_SHR, r1, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */ tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); @@ -845,9 +851,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, tcg_out_mov(s, r0, addr_reg); - tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */ - tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - + tcg_out_shifti(s, SHIFT_SHR, r1, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */ tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); @@ -977,8 +982,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, if (bswap) { tcg_out_mov(s, r1, data_reg); tcg_out8(s, 0x66); /* rolw $8, %ecx */ - tcg_out_modrm(s, 0xc1, 0, r1); - tcg_out8(s, 8); + tcg_out_shifti(s, SHIFT_ROL, r1, 8); data_reg = r1; } /* movw */ @@ -1146,14 +1150,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, c = SHIFT_SHL; gen_shift32: if (const_args[2]) { - if (args[2] == 1) { - tcg_out_modrm(s, 0xd1, c, args[0]); - } else { - tcg_out_modrm(s, 0xc1, c, args[0]); - tcg_out8(s, args[2]); - } + tcg_out_shifti(s, c, args[0], args[2]); } else { - tcg_out_modrm(s, 0xd3, c, args[0]); + tcg_out_modrm(s, OPC_SHIFT_cl, c, args[0]); } break; case INDEX_op_shr_i32: