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Tue, 9 Feb 2016 22:17:30 +0000 Received: from 172-16-1-203.xilinx.com ([172.16.1.203]:35365 helo=xsj-tvapsmtp02.xilinx.com) by xsj-tvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1aTGbB-0002md-CJ; Tue, 09 Feb 2016 14:17:29 -0800 Received: from [127.0.0.1] (port=42584 helo=tsj-smtp-dlp1.xlnx.xilinx.com) by xsj-tvapsmtp02.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1aTGbB-0007aX-67; Tue, 09 Feb 2016 14:17:29 -0800 Received: from xsj-tvapsmtp02 (smtptest.xilinx.com [172.16.1.203]) by tsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id u19MBm1K011557; Tue, 9 Feb 2016 14:11:48 -0800 Received: from [172.19.74.182] (port=49724 helo=xsjalistai50.xlnx.xilinx.com) by xsj-tvapsmtp02 with esmtp (Exim 4.63) (envelope-from ) id 1aTGbA-0007aU-D1; Tue, 09 Feb 2016 14:17:28 -0800 From: Alistair Francis To: , Date: Tue, 9 Feb 2016 14:14:53 -0800 Message-ID: <32e6f2f10d2394ce59543e0fc5f5ef63203cfede.1455055858.git.alistair.francis@xilinx.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: References: X-RCIS-Action: ALLOW X-TM-AS-MML: disable X-TM-AS-Product-Ver: IMSS-7.1.0.1679-8.0.0.1202-22054.006 X-TM-AS-Result: No--9.872-7.0-31-10 X-imss-scan-details: No--9.872-7.0-31-10 X-TMASE-MatchedRID: jedmkgCKCjr/uyguzMmOKFz+axQLnAVB5kzxLgNhSikKogmGusPLb5wl aGGOz9d3SYe0ArCcPhjl0ByOo0JQfYdPogR2+s0tA9lly13c/gGH7D1bP/FcOr/A+0D1to6PbCp JOk5WRE8TWPBg+VFf4DdVfPsjrRvqWU/fB/XFmJx0CDjJ3XioBMSgMQYKGHsJEvoxTu3fj1tVJ0 ADqZV4hhytbxuGVtE6+V+tdy2cWjSdsOWs6DEPXriMC5wdwKqdVxZDTO5gDFObKItl61J/yZ+in TK0bC9eKrauXd3MZDVhVjtTUlKR4LjBOHjSTa8GoB0KFF0hqc8lCgkT8UIQfwfV2w83gFLg X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.96; 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SRVR:BL2NAM02HT016; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT016; X-Forefront-PRVS: 08476BC6EF X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Feb 2016 22:17:30.0416 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.96]; Helo=[xsj-tvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT016 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 104.47.36.76 Cc: edgar.iglesias@xilinx.com, alistair.francis@xilinx.com, crosthwaitepeter@gmail.com, edgar.iglesias@gmail.com, alex.bennee@linaro.org, afaerber@suse.de, fred.konrad@greensocs.com Subject: [Qemu-devel] [PATCH v4 07/16] register: Add block initialise helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite Add a helper that will scan a static RegisterAccessInfo Array and populate a container MemoryRegion with registers as defined. Signed-off-by: Peter Crosthwaite Signed-off-by: Alistair Francis --- V3: - Fix typo V2: - Use memory_region_add_subregion_no_print() hw/core/register.c | 29 +++++++++++++++++++++++++++++ include/hw/register.h | 20 ++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/hw/core/register.c b/hw/core/register.c index d766517..ac866f6 100644 --- a/hw/core/register.c +++ b/hw/core/register.c @@ -210,6 +210,35 @@ uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size) return register_read_memory(opaque, addr, size, false); } +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae, + int num, RegisterInfo *ri, uint32_t *data, + MemoryRegion *container, const MemoryRegionOps *ops, + bool debug_enabled) +{ + const char *debug_prefix = object_get_typename(OBJECT(owner)); + int i; + + for (i = 0; i < num; i++) { + int index = rae[i].decode.addr / 4; + RegisterInfo *r = &ri[index]; + + *r = (RegisterInfo) { + .data = &data[index], + .data_size = sizeof(uint32_t), + .access = &rae[i], + .debug = debug_enabled, + .prefix = debug_prefix, + .opaque = owner, + }; + register_init(r); + + memory_region_init_io(&r->mem, OBJECT(owner), ops, r, r->access->name, + sizeof(uint32_t)); + memory_region_add_subregion_no_print(container, + r->access->decode.addr, &r->mem); + } +} + static const TypeInfo register_info = { .name = TYPE_REGISTER, .parent = TYPE_DEVICE, diff --git a/include/hw/register.h b/include/hw/register.h index d3469c6..6ac005c 100644 --- a/include/hw/register.h +++ b/include/hw/register.h @@ -162,6 +162,26 @@ void register_write_memory_le(void *opaque, hwaddr addr, uint64_t value, uint64_t register_read_memory_be(void *opaque, hwaddr addr, unsigned size); uint64_t register_read_memory_le(void *opaque, hwaddr addr, unsigned size); +/** + * Init a block of consecutive registers into a container MemoryRegion. A + * number of constant register definitions are parsed to create a corresponding + * array of RegisterInfo's. + * + * @owner: device owning the registers + * @rae: Register definitions to init + * @num: number of registers to init (length of @rae) + * @ri: Register array to init + * @data: Array to use for register data + * @container: Memory region to contain new registers + * @ops: Memory region ops to access registers. + * @debug enabled: turn on/off verbose debug information + */ + +void register_init_block32(DeviceState *owner, const RegisterAccessInfo *rae, + int num, RegisterInfo *ri, uint32_t *data, + MemoryRegion *container, const MemoryRegionOps *ops, + bool debug_enabled); + /* Define constants for a 32 bit register */ #define REG32(reg, addr) \ enum { A_ ## reg = (addr) }; \