From patchwork Thu Oct 28 06:54:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 69440 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8F127B6F07 for ; Thu, 28 Oct 2010 18:16:16 +1100 (EST) Received: from localhost ([127.0.0.1]:49287 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PBMib-0002kL-HZ for incoming@patchwork.ozlabs.org; Thu, 28 Oct 2010 03:16:13 -0400 Received: from [140.186.70.92] (port=53166 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PBMVB-0004zB-Vp for qemu-devel@nongnu.org; Thu, 28 Oct 2010 03:02:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PBMNk-0003F2-J0 for qemu-devel@nongnu.org; Thu, 28 Oct 2010 02:54:42 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:54276) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PBMNj-0003EK-Rj for qemu-devel@nongnu.org; Thu, 28 Oct 2010 02:54:40 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 8478E188C0; Thu, 28 Oct 2010 15:54:36 +0900 (JST) Received: (nullmailer pid 7817 invoked by uid 1000); Thu, 28 Oct 2010 06:54:36 -0000 From: Isaku Yamahata To: seabios@seabios.org Date: Thu, 28 Oct 2010 15:54:36 +0900 Message-Id: <31cdbb48626af6ad1d5017538ae03b68c2756439.1288248755.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: yamahata@valinux.co.jp, cam@cs.ualberta.ca, adnan@khaleel.us, qemu-devel@nongnu.org, mst@redhat.com Subject: [Qemu-devel] [PATCH v3 2/2] pciinit: use pci_region functions. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch cleans up pci region allocation with pci_region. Now it is aware of overflow. Signed-off-by: Isaku Yamahata --- Changes v2 -> v3 - pci_region_init() adjustment. --- src/pciinit.c | 122 ++++++++++++++++++++++++++++----------------------------- 1 files changed, 60 insertions(+), 62 deletions(-) diff --git a/src/pciinit.c b/src/pciinit.c index 0346423..795672b 100644 --- a/src/pciinit.c +++ b/src/pciinit.c @@ -17,9 +17,10 @@ static void pci_bios_init_device_in_bus(int bus); -static u32 pci_bios_io_addr; -static u32 pci_bios_mem_addr; -static u32 pci_bios_prefmem_addr; +static struct pci_region pci_bios_io_region; +static struct pci_region pci_bios_mem_region; +static struct pci_region pci_bios_prefmem_region; + /* host irqs corresponding to PCI irqs A-D */ const u8 pci_irqs[4] = { 10, 10, 11, 11 @@ -54,7 +55,7 @@ static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr) */ static int pci_bios_allocate_region(u16 bdf, int region_num) { - u32 *paddr; + struct pci_region *r; u32 ofs = pci_bar(bdf, region_num); u32 old = pci_config_readl(bdf, ofs); @@ -74,41 +75,34 @@ static int pci_bios_allocate_region(u16 bdf, int region_num) u32 size = (~(val & mask)) + 1; if (val != 0) { + const char *type; + const char *msg; if (val & PCI_BASE_ADDRESS_SPACE_IO) { - paddr = &pci_bios_io_addr; - if (ALIGN(*paddr, size) + size >= 64 * 1024) { - dprintf(1, - "io region of (bdf 0x%x bar %d) can't be mapped.\n", - bdf, region_num); - size = 0; - } + r = &pci_bios_io_region; + type = "io"; + msg = ""; } else if ((val & PCI_BASE_ADDRESS_MEM_PREFETCH) && - /* keep behaviour on bus = 0 */ - pci_bdf_to_bus(bdf) != 0 && - /* If pci_bios_prefmem_addr == 0, keep old behaviour */ - pci_bios_prefmem_addr != 0) { - paddr = &pci_bios_prefmem_addr; - if (ALIGN(*paddr, size) + size >= BUILD_PCIPREFMEM_END) { - dprintf(1, - "prefmem region of (bdf 0x%x bar %d) can't be mapped. " - "decrease BUILD_PCIMEM_SIZE and recompile. size %x\n", - bdf, region_num, BUILD_PCIPREFMEM_SIZE); - size = 0; - } + /* keep behaviour on bus = 0 */ + pci_bdf_to_bus(bdf) != 0 && + /* If pci_bios_prefmem_addr == 0, keep old behaviour */ + pci_region_addr(&pci_bios_prefmem_region) != 0) { + r = &pci_bios_prefmem_region; + type = "prefmem"; + msg = "decrease BUILD_PCIMEM_SIZE and recompile. size %x"; } else { - paddr = &pci_bios_mem_addr; - if (ALIGN(*paddr, size) + size >= BUILD_PCIMEM_END) { - dprintf(1, - "mem region of (bdf 0x%x bar %d) can't be mapped. " - "increase BUILD_PCIMEM_SIZE and recompile. size %x\n", - bdf, region_num, BUILD_PCIMEM_SIZE); - size = 0; - } + r = &pci_bios_mem_region; + type = "mem"; + msg = "increase BUILD_PCIMEM_SIZE and recompile."; } - if (size > 0) { - *paddr = ALIGN(*paddr, size); - pci_set_io_region_addr(bdf, region_num, *paddr); - *paddr += size; + u32 addr = pci_region_alloc(r, size); + if (addr > 0) { + pci_set_io_region_addr(bdf, region_num, addr); + } else { + size = 0; + dprintf(1, + "%s region of (bdf 0x%x bar %d) can't be mapped. " + "%s size %x\n", + type, bdf, region_num, msg, pci_region_size(r)); } } @@ -163,33 +157,34 @@ static void pci_bios_init_device_bridge(u16 bdf, void *arg) pci_bios_allocate_region(bdf, 1); pci_bios_allocate_region(bdf, PCI_ROM_SLOT); - u32 io_old = pci_bios_io_addr; - u32 mem_old = pci_bios_mem_addr; - u32 prefmem_old = pci_bios_prefmem_addr; + u32 io_old = pci_region_addr(&pci_bios_io_region); + u32 mem_old = pci_region_addr(&pci_bios_mem_region); + u32 prefmem_old = pci_region_addr(&pci_bios_prefmem_region); /* IO BASE is assumed to be 16 bit */ - pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN); - pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN); - pci_bios_prefmem_addr = - ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN); + if (pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN) == 0) { + pci_region_disable(&pci_bios_io_region); + } + if (pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN) == 0) { + pci_region_disable(&pci_bios_mem_region); + } + if (pci_region_align(&pci_bios_prefmem_region, + PCI_PREF_MEMORY_ALIGN) == 0) { + pci_region_disable(&pci_bios_prefmem_region); + } - u32 io_base = pci_bios_io_addr; - u32 mem_base = pci_bios_mem_addr; - u32 prefmem_base = pci_bios_prefmem_addr; + u32 io_base = pci_region_addr(&pci_bios_io_region); + u32 mem_base = pci_region_addr(&pci_bios_mem_region); + u32 prefmem_base = pci_region_addr(&pci_bios_prefmem_region); u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS); if (secbus > 0) { pci_bios_init_device_in_bus(secbus); } - pci_bios_io_addr = ALIGN(pci_bios_io_addr, PCI_IO_ALIGN); - pci_bios_mem_addr = ALIGN(pci_bios_mem_addr, PCI_MEMORY_ALIGN); - pci_bios_prefmem_addr = - ALIGN(pci_bios_prefmem_addr, PCI_PREF_MEMORY_ALIGN); - - u32 io_end = pci_bios_io_addr; - if (io_end == io_base) { - pci_bios_io_addr = io_old; + u32 io_end = pci_region_align(&pci_bios_io_region, PCI_IO_ALIGN); + if (io_end == 0) { + pci_region_revert(&pci_bios_io_region, io_old); io_base = 0xffff; io_end = 1; } @@ -198,18 +193,19 @@ static void pci_bios_init_device_bridge(u16 bdf, void *arg) pci_config_writeb(bdf, PCI_IO_LIMIT, (io_end - 1) >> PCI_IO_SHIFT); pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0); - u32 mem_end = pci_bios_mem_addr; - if (mem_end == mem_base) { - pci_bios_mem_addr = mem_old; + u32 mem_end = pci_region_align(&pci_bios_mem_region, PCI_MEMORY_ALIGN); + if (mem_end == 0) { + pci_region_revert(&pci_bios_mem_region, mem_old); mem_base = 0xffffffff; mem_end = 1; } pci_config_writew(bdf, PCI_MEMORY_BASE, mem_base >> PCI_MEMORY_SHIFT); pci_config_writew(bdf, PCI_MEMORY_LIMIT, (mem_end -1) >> PCI_MEMORY_SHIFT); - u32 prefmem_end = pci_bios_prefmem_addr; - if (prefmem_end == prefmem_base) { - pci_bios_prefmem_addr = prefmem_old; + u32 prefmem_end = pci_region_align(&pci_bios_prefmem_region, + PCI_PREF_MEMORY_ALIGN); + if (prefmem_end == 0) { + pci_region_revert(&pci_bios_prefmem_region, prefmem_old); prefmem_base = 0xffffffff; prefmem_end = 1; } @@ -406,9 +402,11 @@ pci_setup(void) dprintf(3, "pci setup\n"); - pci_bios_io_addr = 0xc000; - pci_bios_mem_addr = BUILD_PCIMEM_START; - pci_bios_prefmem_addr = BUILD_PCIPREFMEM_START; + pci_region_init(&pci_bios_io_region, 0xc000, 64 * 1024); + pci_region_init(&pci_bios_mem_region, + BUILD_PCIMEM_START, BUILD_PCIMEM_END - 1); + pci_region_init(&pci_bios_prefmem_region, + BUILD_PCIPREFMEM_START, BUILD_PCIPREFMEM_END - 1); pci_bios_init_bus();