From patchwork Tue May 10 13:24:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Imran, Talha" X-Patchwork-Id: 620632 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r40Nc4Dnzz9t45 for ; Tue, 10 May 2016 23:25:04 +1000 (AEST) Received: from localhost ([::1]:46284 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b07eo-0006xX-LX for incoming@patchwork.ozlabs.org; Tue, 10 May 2016 09:25:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b07eV-0006Oc-Mx for qemu-devel@nongnu.org; Tue, 10 May 2016 09:24:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b07eO-0004iL-Af for qemu-devel@nongnu.org; Tue, 10 May 2016 09:24:42 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:46429) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b07eJ-0004eh-8u; Tue, 10 May 2016 09:24:31 -0400 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-02.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1b07e8-0006m1-Qi from Talha_Imran@mentor.com ; Tue, 10 May 2016 06:24:21 -0700 Received: from EU-MBX-02.mgc.mentorg.com ([169.254.3.121]) by SVR-IES-FEM-02.mgc.mentorg.com ([137.202.0.106]) with mapi id 14.03.0224.002; Tue, 10 May 2016 14:24:19 +0100 From: "Imran, Talha" To: "qemu-ppc@nongnu.org" , "qemu-devel@nongnu.org" Thread-Topic: [PATCH] Fix QEMU PPC e500v1 efscmp* instructions Thread-Index: AQHRqr9BoGiDdbboj0abVCg4qfVMbA== Date: Tue, 10 May 2016 13:24:19 +0000 Message-ID: <3052678E9DA67D4CB879A6625EE42075274B5092@EU-MBX-02.mgc.mentorg.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [137.202.0.69] MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: [Qemu-devel] [PATCH] Fix QEMU PPC e500v1 efscmp* instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Hi Everyone, Please find attached a patch which fixes handling in QEMU PPC e500v1 for efscmp* instructions. This was the cause of over 400 FAILs for this CPU while running GCC testsuite, which have been fixed. Value for Condition Registers (CR) being set in QEMU was different from the value observed on hardware. I have not managed to find a documentation describing the behaviour of e500 cores for these instructions. However, the behaviour on MPC8548-CDS target was observed by dumping registers to stdout, while running executables from uboot. These instructions are used by GCC only when compiling for te500v1 multilib; hence no effect on other PPC CPUs (603, 7400 etc.) A comparison of GCC v5.2.0 testsuite results summary (number of FAILs) is as follows: CPU = te500v1 without patch: 699 with patch: 193 CPU = e500v2 without patch: 225 with patch: 225 Is this OK to commit? Comments and suggestions are welcome. Thanks, Talha Imran diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index b67ebca..752c552 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1400,7 +1400,7 @@ static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2) u1.l = op1; u2.l = op2; - return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0; + return float32_lt(u1.f, u2.f, &env->vec_status) ? 6 : 0; } static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2) @@ -1409,7 +1409,7 @@ static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2) u1.l = op1; u2.l = op2; - return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4; + return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 6; } static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2) @@ -1418,7 +1418,7 @@ static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2) u1.l = op1; u2.l = op2; - return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0; + return float32_eq(u1.f, u2.f, &env->vec_status) ? 6 : 0; } static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2) @@ -1442,7 +1442,7 @@ static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2) #define HELPER_SINGLE_SPE_CMP(name) \ uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \ { \ - return e##name(env, op1, op2) << 2; \ + return e##name(env, op1, op2); \ } /* efststlt */ HELPER_SINGLE_SPE_CMP(fststlt);