| Message ID | 2a4a27e9b27f0e75052fc52f36449e397fd5a65d.1290160397.git.yamahata@valinux.co.jp |
|---|---|
| State | New |
| Headers | show |
On Fri, Nov 19, 2010 at 06:56:03PM +0900, Isaku Yamahata wrote: > Emulates secondary bus reset when secondary bus reset bit > is written from 0 to 1. > Interesting. This is not exactly what happens on real hardware though: there, RST# stays asserted until bit is cleared. So for example attempts to scan the secondary bus will return nothing. Can implement this later, but please add a comment here. > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> > Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> > --- > hw/pci_bridge.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > index 58cc2e4..618a81e 100644 > --- a/hw/pci_bridge.c > +++ b/hw/pci_bridge.c > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) > void pci_bridge_write_config(PCIDevice *d, > uint32_t address, uint32_t val, int len) > { > + PCIBridge *s = container_of(d, PCIBridge, dev); > + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + uint16_t bridge_control_new; I'd prefer shorter names for local variables. > + > pci_default_write_config(d, address, val, len); > > if (/* io base/limit */ > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, > /* memory base/limit, prefetchable base/limit and > io base/limit upper 16 */ > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > - PCIBridge *s = container_of(d, PCIBridge, dev); > pci_bridge_update_mappings(&s->sec_bus); > } > + > + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { Equivalent but shorter: ~bridge_control & bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET > + /* 0 -> 1 */ > + pci_bus_reset(&s->sec_bus); > + } > } > > void pci_bridge_disable_base_limit(PCIDevice *dev) > -- > 1.7.1.1
diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c index 58cc2e4..618a81e 100644 --- a/hw/pci_bridge.c +++ b/hw/pci_bridge.c @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) void pci_bridge_write_config(PCIDevice *d, uint32_t address, uint32_t val, int len) { + PCIBridge *s = container_of(d, PCIBridge, dev); + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); + uint16_t bridge_control_new; + pci_default_write_config(d, address, val, len); if (/* io base/limit */ @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, /* memory base/limit, prefetchable base/limit and io base/limit upper 16 */ ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { - PCIBridge *s = container_of(d, PCIBridge, dev); pci_bridge_update_mappings(&s->sec_bus); } + + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { + /* 0 -> 1 */ + pci_bus_reset(&s->sec_bus); + } } void pci_bridge_disable_base_limit(PCIDevice *dev)