From patchwork Wed Oct 20 08:19:01 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 68405 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 85EB1B70D4 for ; Wed, 20 Oct 2010 19:52:29 +1100 (EST) Received: from localhost ([127.0.0.1]:51058 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P8UPI-00039A-Ud for incoming@patchwork.ozlabs.org; Wed, 20 Oct 2010 04:52:24 -0400 Received: from [140.186.70.92] (port=43725 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P8Tyi-0004Ai-Vt for qemu-devel@nongnu.org; Wed, 20 Oct 2010 04:25:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P8Tt4-0000WA-6C for qemu-devel@nongnu.org; Wed, 20 Oct 2010 04:19:07 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:46415) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P8Tt3-0000VX-N5 for qemu-devel@nongnu.org; Wed, 20 Oct 2010 04:19:06 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id 16F26873D3; Wed, 20 Oct 2010 17:19:03 +0900 (JST) Received: (nullmailer pid 20066 invoked by uid 1000); Wed, 20 Oct 2010 08:19:01 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Wed, 20 Oct 2010 17:19:01 +0900 Message-Id: <22861084c7500bc73e9199bf9568014a4be85f09.1287562197.git.yamahata@valinux.co.jp> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, adnan@khaleel.us, wexu2@cisco.com, mst@redhat.com, yamahata@valinux.co.jp, etmartin@cisco.com Subject: [Qemu-devel] [PATCH v6 12/12] x3130/downstream: support aer. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org add aer support. Signed-off-by: Isaku Yamahata --- hw/xio3130_downstream.c | 15 ++++++++++----- 1 files changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c index a44e188..9087c0b 100644 --- a/hw/xio3130_downstream.c +++ b/hw/xio3130_downstream.c @@ -40,12 +40,14 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, { uint16_t sltctl = pci_get_word(d->config + d->exp.exp_cap + PCI_EXP_SLTCTL); + uint32_t uncorsta = + pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_UNCOR_STATUS); pci_bridge_write_config(d, address, val, len); pcie_cap_flr_write_config(d, address, val, len); pcie_cap_slot_write_config(d, address, val, len, sltctl); msi_write_config(d, address, val, len); - /* TODO: AER */ + pcie_aer_write_config(d, address, val, len, uncorsta); } static void xio3130_downstream_reset(DeviceState *qdev) @@ -100,14 +102,14 @@ static int xio3130_downstream_initfn(PCIDevice *d) return rc; } pcie_cap_ari_init(d); - /* TODO: AER */ + pcie_aer_init(d, XIO3130_AER_OFFSET); return 0; } static int xio3130_downstream_exitfn(PCIDevice *d) { - /* TODO: AER */ + pcie_aer_exit(d); msi_uninit(d); pcie_cap_exit(d); return pci_bridge_exitfn(d); @@ -146,7 +148,8 @@ static const VMStateDescription vmstate_xio3130_downstream = { .minimum_version_id_old = 1, .fields = (VMStateField[]) { VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), - /* TODO: AER */ + VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, + vmstate_pcie_aer_log, PCIEAERLog), VMSTATE_END_OF_LIST() } }; @@ -168,7 +171,9 @@ static PCIDeviceInfo xio3130_downstream_info = { DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), - /* TODO: AER */ + DEFINE_PROP_UINT16("aer_log_max", PCIESlot, + port.br.dev.exp.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), DEFINE_PROP_END_OF_LIST(), } };