[PULL,47/50] docs/specs: add riscv-iommu

Message ID	20241031035319.731906-48-alistair.francis@wdc.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Alistair Francis <alistair23@gmail.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com> Subject: [PULL 47/50] docs/specs: add riscv-iommu Date: Thu, 31 Oct 2024 13:53:15 +1000 Message-ID: <20241031035319.731906-48-alistair.francis@wdc.com> In-Reply-To: <20241031035319.731906-1-alistair.francis@wdc.com> References: <20241031035319.731906-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	[PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT \| expand [PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT [PULL,02/50] target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI [PULL,03/50] target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32 [PULL,04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU [PULL,05/50] target/riscv: Detect sxl to set bit width for RV32 in RV64 [PULL,06/50] target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU [PULL,07/50] target/riscv: Enable RV32 CPU support in RV64 QEMU [PULL,08/50] target/riscv: Add max32 CPU for RV64 QEMU [PULL,09/50] tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU [PULL,10/50] hw/intc: Make zeroth priority register read-only [PULL,11/50] hw/intc: Don't clear pending bits on IRQ lowering [PULL,12/50] target/riscv: Set vtype.vill on CPU reset [PULL,13/50] hw/intc/riscv_aplic: Check and update pending when write sourcecfg [PULL,14/50] hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all [PULL,15/50] hw/char: sifive_uart: Print uart characters async [PULL,16/50] target/riscv: expose *envcfg csr and priv to qemu-user as well [PULL,17/50] target/riscv: Add zicfilp extension [PULL,18/50] target/riscv: Introduce elp state and enabling controls for zicfilp [PULL,19/50] target/riscv: save and restore elp state on priv transitions [PULL,20/50] target/riscv: additional code information for sw check [PULL,21/50] target/riscv: tracking indirect branches (fcfi) for zicfilp [PULL,22/50] target/riscv: zicfilp `lpad` impl and branch tracking [PULL,23/50] disas/riscv: enable `lpad` disassembly [PULL,24/50] target/riscv: Expose zicfilp extension as a cpu property [PULL,25/50] target/riscv: Add zicfiss extension [PULL,26/50] target/riscv: introduce ssp and enabling controls for zicfiss [PULL,27/50] target/riscv: tb flag for shadow stack instructions [PULL,28/50] target/riscv: mmu changes for zicfiss shadow stack protection [PULL,29/50] target/riscv: AMO operations always raise store/AMO fault [PULL,30/50] target/riscv: update `decode_save_opc` to store extra word2 [PULL,31/50] target/riscv: implement zicfiss instructions [PULL,32/50] target/riscv: compressed encodings for sspush and sspopchk [PULL,33/50] disas/riscv: enable disassembly for zicfiss instructions [PULL,34/50] disas/riscv: enable disassembly for compressed sspush/sspopchk [PULL,35/50] target/riscv: Expose zicfiss extension as a cpu property [PULL,36/50] exec/memtxattr: add process identifier to the transaction attributes [PULL,37/50] hw/riscv: add riscv-iommu-bits.h [PULL,38/50] hw/riscv: add RISC-V IOMMU base emulation [PULL,39/50] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device [PULL,40/50] hw/riscv: add riscv-iommu-pci reference device [PULL,41/50] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug [PULL,42/50] test/qtest: add riscv-iommu-pci tests [PULL,43/50] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) [PULL,44/50] hw/riscv/riscv-iommu: add ATS support [PULL,45/50] hw/riscv/riscv-iommu: add DBG support [PULL,46/50] qtest/riscv-iommu-test: add init queues test [PULL,47/50] docs/specs: add riscv-iommu [PULL,48/50] target/riscv/kvm: set 'aia_mode' to default in error path [PULL,49/50] target/riscv/kvm: clarify how 'riscv-aia' default works [PULL,50/50] target/riscv: Fix vcompress with rvv_ta_all_1s

Message ID

20241031035319.731906-48-alistair.francis@wdc.com

State

New

Headers

From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
 Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 47/50] docs/specs: add riscv-iommu
Date: Thu, 31 Oct 2024 13:53:15 +1000
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Series

[PULL,01/50] target/riscv/csr.c: Fix an access to VXSAT | expand

Commit Message

Alistair Francis Oct. 31, 2024, 3:53 a.m. UTC

From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Add a simple guideline to use the existing RISC-V IOMMU support we just
added.

This doc will be updated once we add the riscv-iommu-sys device.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241016204038.649340-13-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 docs/specs/index.rst       |  1 +
 docs/specs/riscv-iommu.rst | 90 ++++++++++++++++++++++++++++++++++++++
 docs/system/riscv/virt.rst | 13 ++++++
 3 files changed, 104 insertions(+)
 create mode 100644 docs/specs/riscv-iommu.rst

diff --git a/docs/specs/index.rst b/docs/specs/index.rst
index 6495ed5ed9..ff5a1f03da 100644
--- a/docs/specs/index.rst
+++ b/docs/specs/index.rst
@@ -36,3 +36,4 @@  guest hardware that is specific to QEMU.
    vmgenid
    rapl-msr
    rocker
+   riscv-iommu
diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst
new file mode 100644
index 0000000000..463f4cffb6
--- /dev/null
+++ b/docs/specs/riscv-iommu.rst
@@ -0,0 +1,90 @@ 
+.. _riscv-iommu:
+
+RISC-V IOMMU support for RISC-V machines
+========================================
+
+QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
+version 1.0 `iommu1.0`_.
+
+The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
+RISC-V boards can use.  The 'virt' RISC-V machine is compatible with this
+device.
+
+riscv-iommu-pci reference device
+--------------------------------
+
+This device implements the RISC-V IOMMU emulation as recommended by the section
+"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base
+class 08h, sub-class 06h and programming interface 00h.
+
+As a reference device it doesn't implement anything outside of the specification,
+so it uses a generic default PCI ID given by QEMU: 1b36:0014.
+
+To include the device in the 'virt' machine:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt -device riscv-iommu-pci,[optional_pci_opts] (...)
+
+This will add a RISC-V IOMMU PCI device in the board following any additional
+PCI parameters (like PCI bus address).  The behavior of the RISC-V IOMMU is
+defined by the spec but its operation is OS dependent.
+
+As of this writing the existing Linux kernel support `linux-v8`_, not yet merged,
+does not have support for features like VFIO passthrough.  The IOMMU emulation
+was tested using a public Ventana Micro Systems kernel repository in
+`ventana-linux`_.  This kernel is based on `linux-v8`_ with additional patches that
+enable features like KVM VFIO passthrough with irqbypass.  Until the kernel support
+is feature complete feel free to use the kernel available in the Ventana Micro Systems
+mirror.
+
+The current Linux kernel support will use the IOMMU device to create IOMMU groups
+with any eligible cards available in the system, regardless of factors such as the
+order in which the devices are added in the command line.
+
+This means that these command lines are equivalent as far as the current
+IOMMU kernel driver behaves:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 \
+        -M virt,aia=aplic-imsic,aia-guests=5 \
+        -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \
+        -device e1000e,netdev=net1 -netdev user,id=net1,net=192.168.0.0/24 \
+        -device e1000e,netdev=net2 -netdev user,id=net2,net=192.168.200.0/24 \
+        (...)
+
+  $ qemu-system-riscv64 \
+        -M virt,aia=aplic-imsic,aia-guests=5 \
+        -device e1000e,netdev=net1 -netdev user,id=net1,net=192.168.0.0/24 \
+        -device e1000e,netdev=net2 -netdev user,id=net2,net=192.168.200.0/24 \
+        -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \
+        (...)
+
+Both will create iommu groups for the two e1000e cards.
+
+Another thing to notice on `linux-v8`_ and `ventana-linux`_ is that the kernel driver
+considers an IOMMU identified as a Rivos device, i.e. it uses Rivos vendor ID.  To
+use the riscv-iommu-pci device with the existing kernel support we need to emulate
+a Rivos PCI IOMMU by setting 'vendor-id' and 'device-id':
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt	\
+     -device riscv-iommu-pci,vendor-id=0x1efd,device-id=0xedf1 (...)
+
+Several options are available to control the capabilities of the device, namely:
+
+- "bus": the bus that the IOMMU device uses
+- "ioatc-limit": size of the Address Translation Cache (default to 2Mb)
+- "intremap": enable/disable MSI support
+- "ats": enable ATS support
+- "off" (Out-of-reset translation mode: 'on' for DMA disabled, 'off' for 'BARE' (passthrough))
+- "s-stage": enable s-stage support
+- "g-stage": enable g-stage support
+
+.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
+
+.. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/
+
+.. _ventana-linux: https://github.com/ventanamicro/linux/tree/dev-upstream
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 9a06f95a34..8e9a2e4dda 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -84,6 +84,19 @@  none``, as in
 
 Firmware images used for pflash must be exactly 32 MiB in size.
 
+riscv-iommu support
+-------------------
+
+The board has support for the riscv-iommu-pci device by using the following
+command line:
+
+.. code-block:: bash
+
+  $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...)
+
+Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU support
+works.
+
 Machine-specific options
 ------------------------

[PULL,47/50] docs/specs: add riscv-iommu

Commit Message

Patch