[v3,15/17] bsd-user: Implement 'get_mcontext' for RISC-V

Message ID	20240824045635.8978-16-itachis@FreeBSD.org
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Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Ajeet Singh <itachis6234@gmail.com> To: qemu-devel@nongnu.org Cc: Warner Losh <imp@bsdimp.com>, Mark Corbin <mark@dibsco.co.uk>, Ajeet Singh <itachis@FreeBSD.org>, Richard Henderson <richard.henderson@linaro.org> Subject: [PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Date: Sat, 24 Aug 2024 14:56:33 +1000 Message-Id: <20240824045635.8978-16-itachis@FreeBSD.org> In-Reply-To: <20240824045635.8978-1-itachis@FreeBSD.org> References: <20240824045635.8978-1-itachis@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=itachis6234@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	bsd-user: Comprehensive RISCV Support \| expand [v3,00/17] bsd-user: Comprehensive RISCV Support [v3,01/17] bsd-user: Implement RISC-V CPU initialization and main loop [v3,02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling [v3,03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions [v3,04/17] bsd-user: Implement RISC-V TLS register setup [v3,05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection [v3,06/17] bsd-user: Define RISC-V register structures and register copying [v3,07/17] bsd-user: Add RISC-V signal trampoline setup function [v3,08/17] bsd-user: Implement RISC-V sysarch system call emulation [v3,09/17] bsd-user: Add RISC-V thread setup and initialization support [v3,10/17] bsd-user: Define RISC-V VM parameters and helper functions [v3,11/17] bsd-user: Define RISC-V system call structures and constants [v3,12/17] bsd-user: Add generic RISC-V64 target definitions [v3,13/17] bsd-user: Define RISC-V signal handling structures and constants [v3,14/17] bsd-user: Implement RISC-V signal trampoline setup functions [v3,15/17] bsd-user: Implement 'get_mcontext' for RISC-V [v3,16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV [v3,17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files

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20240824045635.8978-16-itachis@FreeBSD.org

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New

Headers

From: Ajeet Singh <itachis6234@gmail.com>
To: qemu-devel@nongnu.org
Cc: Warner Losh <imp@bsdimp.com>, Mark Corbin <mark@dibsco.co.uk>,
 Ajeet Singh <itachis@FreeBSD.org>,
 Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V
Date: Sat, 24 Aug 2024 14:56:33 +1000
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Series

bsd-user: Comprehensive RISCV Support | expand

Commit Message

Ajeet Singh Aug. 24, 2024, 4:56 a.m. UTC

From: Mark Corbin <mark@dibsco.co.uk>

Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.

Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Signed-off-by: Warner Losh <imp@bsdimp.com>
Co-authored-by: Warner Losh <imp@bsdimp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 bsd-user/riscv/signal.c | 53 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/bsd-user/riscv/signal.c b/bsd-user/riscv/signal.c
index 2597fec2fd..072ad821d2 100644
--- a/bsd-user/riscv/signal.c
+++ b/bsd-user/riscv/signal.c
@@ -61,3 +61,56 @@  abi_long setup_sigframe_arch(CPURISCVState *env, abi_ulong frame_addr,
     get_mcontext(env, mcp, flags);
     return 0;
 }
+
+/*
+ * Compare with get_mcontext() in riscv/riscv/machdep.c
+ * Assumes that the memory is locked if mcp points to user memory.
+ */
+abi_long get_mcontext(CPURISCVState *regs, target_mcontext_t *mcp,
+        int flags)
+{
+
+    mcp->mc_gpregs.gp_t[0] = tswap64(regs->gpr[5]);
+    mcp->mc_gpregs.gp_t[1] = tswap64(regs->gpr[6]);
+    mcp->mc_gpregs.gp_t[2] = tswap64(regs->gpr[7]);
+    mcp->mc_gpregs.gp_t[3] = tswap64(regs->gpr[28]);
+    mcp->mc_gpregs.gp_t[4] = tswap64(regs->gpr[29]);
+    mcp->mc_gpregs.gp_t[5] = tswap64(regs->gpr[30]);
+    mcp->mc_gpregs.gp_t[6] = tswap64(regs->gpr[31]);
+
+    mcp->mc_gpregs.gp_s[0] = tswap64(regs->gpr[8]);
+    mcp->mc_gpregs.gp_s[1] = tswap64(regs->gpr[9]);
+    mcp->mc_gpregs.gp_s[2] = tswap64(regs->gpr[18]);
+    mcp->mc_gpregs.gp_s[3] = tswap64(regs->gpr[19]);
+    mcp->mc_gpregs.gp_s[4] = tswap64(regs->gpr[20]);
+    mcp->mc_gpregs.gp_s[5] = tswap64(regs->gpr[21]);
+    mcp->mc_gpregs.gp_s[6] = tswap64(regs->gpr[22]);
+    mcp->mc_gpregs.gp_s[7] = tswap64(regs->gpr[23]);
+    mcp->mc_gpregs.gp_s[8] = tswap64(regs->gpr[24]);
+    mcp->mc_gpregs.gp_s[9] = tswap64(regs->gpr[25]);
+    mcp->mc_gpregs.gp_s[10] = tswap64(regs->gpr[26]);
+    mcp->mc_gpregs.gp_s[11] = tswap64(regs->gpr[27]);
+
+    mcp->mc_gpregs.gp_a[0] = tswap64(regs->gpr[10]);
+    mcp->mc_gpregs.gp_a[1] = tswap64(regs->gpr[11]);
+    mcp->mc_gpregs.gp_a[2] = tswap64(regs->gpr[12]);
+    mcp->mc_gpregs.gp_a[3] = tswap64(regs->gpr[13]);
+    mcp->mc_gpregs.gp_a[4] = tswap64(regs->gpr[14]);
+    mcp->mc_gpregs.gp_a[5] = tswap64(regs->gpr[15]);
+    mcp->mc_gpregs.gp_a[6] = tswap64(regs->gpr[16]);
+    mcp->mc_gpregs.gp_a[7] = tswap64(regs->gpr[17]);
+
+    if (flags & TARGET_MC_GET_CLEAR_RET) {
+        mcp->mc_gpregs.gp_a[0] = 0; /* a0 */
+        mcp->mc_gpregs.gp_a[1] = 0; /* a1 */
+        mcp->mc_gpregs.gp_t[0] = 0; /* clear syscall error */
+    }
+
+    mcp->mc_gpregs.gp_ra = tswap64(regs->gpr[1]);
+    mcp->mc_gpregs.gp_sp = tswap64(regs->gpr[2]);
+    mcp->mc_gpregs.gp_gp = tswap64(regs->gpr[3]);
+    mcp->mc_gpregs.gp_tp = tswap64(regs->gpr[4]);
+    mcp->mc_gpregs.gp_sepc = tswap64(regs->pc);
+
+    return 0;
+}

[v3,15/17] bsd-user: Implement 'get_mcontext' for RISC-V

Commit Message

Patch