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Tue, 11 Jun 2024 07:26:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGgut4qL3MC09PLBQDbHWHIPaYXuYJfJDrJue/7KFLIDTwQ2C+TcxMh/erwbEdlh5KGv0larA== X-Received: by 2002:a50:d712:0:b0:579:e6ff:c61f with SMTP id 4fb4d7f45d1cf-57c508fd7f6mr11778532a12.25.1718115968845; Tue, 11 Jun 2024 07:26:08 -0700 (PDT) Received: from avogadro.local ([151.62.196.71]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57c8e5a77d6sm2272051a12.0.2024.06.11.07.26.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Jun 2024 07:26:06 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 20/25] target/i386: adapt gen_shift_count for SHLD/SHRD Date: Tue, 11 Jun 2024 16:25:18 +0200 Message-ID: <20240611142524.83762-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240611142524.83762-1-pbonzini@redhat.com> References: <20240611142524.83762-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.141, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either 1 or CL - and therefore decode->op[2] is taken by the low part of the register being shifted. Pass X86_OP_* to gen_shift_count from its current callers and hardcode cpu_regs[R_ECX] as the shift count. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/emit.c.inc | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 92635f53cf4..156ea282af4 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -2874,16 +2874,16 @@ static void gen_PUSHF(DisasContext *s, X86DecodedInsn *decode) } static MemOp gen_shift_count(DisasContext *s, X86DecodedInsn *decode, - bool *can_be_zero, TCGv *count) + bool *can_be_zero, TCGv *count, int unit) { MemOp ot = decode->op[0].ot; int mask = (ot <= MO_32 ? 0x1f : 0x3f); *can_be_zero = false; - switch (decode->op[2].unit) { + switch (unit) { case X86_OP_INT: *count = tcg_temp_new(); - tcg_gen_andi_tl(*count, s->T1, mask); + tcg_gen_andi_tl(*count, cpu_regs[R_ECX], mask); *can_be_zero = true; break; @@ -3068,7 +3068,7 @@ static void gen_RCL(DisasContext *s, X86DecodedInsn *decode) bool have_1bit_cin, can_be_zero; TCGv count; TCGLabel *zero_label = NULL; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv low, high, low_count; if (!count) { @@ -3120,7 +3120,7 @@ static void gen_RCR(DisasContext *s, X86DecodedInsn *decode) bool have_1bit_cin, can_be_zero; TCGv count; TCGLabel *zero_label = NULL; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv low, high, high_count; if (!count) { @@ -3298,7 +3298,7 @@ static void gen_ROL(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv_i32 temp32, count32; TCGv old = tcg_temp_new(); @@ -3326,7 +3326,7 @@ static void gen_ROR(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); TCGv_i32 temp32, count32; TCGv old = tcg_temp_new(); @@ -3438,7 +3438,7 @@ static void gen_SAR(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); if (!count) { return; @@ -3566,7 +3566,7 @@ static void gen_SHL(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); if (!count) { return; @@ -3598,7 +3598,7 @@ static void gen_SHR(DisasContext *s, X86DecodedInsn *decode) { bool can_be_zero; TCGv count; - MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count); + MemOp ot = gen_shift_count(s, decode, &can_be_zero, &count, decode->op[2].unit); if (!count) { return;