| Message ID | 20240531202759.911601-8-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/riscv/virt.c: aplic/imsic DT fixes | expand |
On Sat, Jun 1, 2024 at 6:31 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the > 'compatible' property. > > [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml > > Reported-by: Conor Dooley <conor@kernel.org> > Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/virt.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 56d7e945c6..ac70993679 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -515,6 +515,9 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, > uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; > g_autofree uint32_t *imsic_cells = NULL; > g_autofree uint32_t *imsic_regs = NULL; > + static const char * const imsic_compat[2] = { > + "qemu,imsics", "riscv,imsics" > + }; > > imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); > imsic_regs = g_new0(uint32_t, socket_count * 4); > @@ -541,7 +544,10 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, > imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", > (unsigned long)base_addr); > qemu_fdt_add_subnode(ms->fdt, imsic_name); > - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); > + qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", > + (char **)&imsic_compat, > + ARRAY_SIZE(imsic_compat)); > + > qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", > FDT_IMSIC_INT_CELLS); > qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); > -- > 2.45.1 > >
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 56d7e945c6..ac70993679 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -515,6 +515,9 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, uint32_t imsic_max_hart_per_socket, imsic_addr, imsic_size; g_autofree uint32_t *imsic_cells = NULL; g_autofree uint32_t *imsic_regs = NULL; + static const char * const imsic_compat[2] = { + "qemu,imsics", "riscv,imsics" + }; imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs = g_new0(uint32_t, socket_count * 4); @@ -541,7 +544,10 @@ static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, imsic_name = g_strdup_printf("/soc/interrupt-controller@%lx", (unsigned long)base_addr); qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); + qemu_fdt_setprop_string_array(ms->fdt, imsic_name, "compatible", + (char **)&imsic_compat, + ARRAY_SIZE(imsic_compat)); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0);
The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the 'compatible' property. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- hw/riscv/virt.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)