diff mbox series

[v2,53/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec

Message ID	20240524232121.284515-54-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 53/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec Date: Fri, 24 May 2024 16:21:07 -0700 Message-Id: <20240524232121.284515-54-richard.henderson@linaro.org> In-Reply-To: <20240524232121.284515-1-richard.henderson@linaro.org> References: <20240524232121.284515-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Series	target/arm: Convert a64 advsimd to decodetree (part 1) \| expand [v2,00/67] target/arm: Convert a64 advsimd to decodetree (part 1) [v2,01/67] target/arm: Add neoverse-n1 to qemu-arm (DO NOT MERGE) [v2,02/67] target/arm: Use PLD, PLDW, PLI not NOP for t32 [v2,03/67] target/arm: Reject incorrect operands to PLD, PLDW, PLI [v2,04/67] target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer) [v2,05/67] target/arm: Fix decode of FMOV (hp) vs MOVI [v2,06/67] target/arm: Verify sz=0 for Advanced SIMD scalar pairwise (fp16) [v2,07/67] target/arm: Split out gengvec.c [v2,08/67] target/arm: Split out gengvec64.c [v2,09/67] target/arm: Convert Cryptographic AES to decodetree [v2,10/67] target/arm: Convert Cryptographic 3-register SHA to decodetree [v2,11/67] target/arm: Convert Cryptographic 2-register SHA to decodetree [v2,12/67] target/arm: Convert Cryptographic 3-register SHA512 to decodetree [v2,13/67] target/arm: Convert Cryptographic 2-register SHA512 to decodetree [v2,14/67] target/arm: Convert Cryptographic 4-register to decodetree [v2,15/67] target/arm: Convert Cryptographic 3-register, imm2 to decodetree [v2,16/67] target/arm: Convert XAR to decodetree [v2,17/67] target/arm: Convert Advanced SIMD copy to decodetree [v2,18/67] target/arm: Convert FMULX to decodetree [v2,19/67] target/arm: Convert FADD, FSUB, FDIV, FMUL to decodetree [v2,20/67] target/arm: Convert FMAX, FMIN, FMAXNM, FMINNM to decodetree [v2,21/67] target/arm: Introduce vfp_load_reg16 [v2,22/67] target/arm: Expand vfp neg and abs inline [v2,23/67] target/arm: Convert FNMUL to decodetree [v2,24/67] target/arm: Convert FMLA, FMLS to decodetree [v2,25/67] target/arm: Convert FCMEQ, FCMGE, FCMGT, FACGE, FACGT to decodetree [v2,26/67] target/arm: Convert FABD to decodetree [v2,27/67] target/arm: Convert FRECPS, FRSQRTS to decodetree [v2,28/67] target/arm: Convert FADDP to decodetree [v2,29/67] target/arm: Convert FMAXP, FMINP, FMAXNMP, FMINNMP to decodetree [v2,30/67] target/arm: Use gvec for neon faddp, fmaxp, fminp [v2,31/67] target/arm: Convert ADDP to decodetree [v2,32/67] target/arm: Use gvec for neon padd [v2,33/67] target/arm: Convert SMAXP, SMINP, UMAXP, UMINP to decodetree [v2,34/67] target/arm: Use gvec for neon pmax, pmin [v2,35/67] target/arm: Convert FMLAL, FMLSL to decodetree [v2,36/67] target/arm: Convert disas_simd_3same_logic to decodetree [v2,37/67] target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB [v2,38/67] target/arm: Convert SUQADD and USQADD to gvec [v2,39/67] target/arm: Inline scalar SUQADD and USQADD [v2,40/67] target/arm: Inline scalar SQADD, UQADD, SQSUB, UQSUB [v2,41/67] target/arm: Convert SQADD, SQSUB, UQADD, UQSUB to decodetree [v2,42/67] target/arm: Convert SUQADD, USQADD to decodetree [v2,43/67] target/arm: Convert SSHL, USHL to decodetree [v2,44/67] target/arm: Convert SRSHL and URSHL (register) to gvec [v2,45/67] target/arm: Convert SRSHL, URSHL to decodetree [v2,46/67] target/arm: Convert SQSHL and UQSHL (register) to gvec [v2,47/67] target/arm: Convert SQSHL, UQSHL to decodetree [v2,48/67] target/arm: Convert SQRSHL and UQRSHL (register) to gvec [v2,49/67] target/arm: Convert SQRSHL, UQRSHL to decodetree [v2,50/67] target/arm: Convert ADD, SUB (vector) to decodetree [v2,51/67] target/arm: Convert CMGT, CMHI, CMGE, CMHS, CMTST, CMEQ to decodetree [v2,52/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_{i32, i64} [v2,53/67] target/arm: Use TCG_COND_TSTNE in gen_cmtst_vec [v2,54/67] target/arm: Convert SHADD, UHADD to gvec [v2,55/67] target/arm: Convert SHADD, UHADD to decodetree [v2,56/67] target/arm: Convert SHSUB, UHSUB to gvec [v2,57/67] target/arm: Convert SHSUB, UHSUB to decodetree [v2,58/67] target/arm: Convert SRHADD, URHADD to gvec [v2,59/67] target/arm: Convert SRHADD, URHADD to decodetree [v2,60/67] target/arm: Convert SMAX, SMIN, UMAX, UMIN to decodetree [v2,61/67] target/arm: Convert SABA, SABD, UABA, UABD to decodetree [v2,62/67] target/arm: Convert MUL, PMUL to decodetree [v2,63/67] target/arm: Convert MLA, MLS to decodetree [v2,64/67] target/arm: Tidy SQDMULH, SQRDMULH (vector) [v2,65/67] target/arm: Convert SQDMULH, SQRDMULH to decodetree [v2,66/67] target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree [v2,67/67] target/arm: Convert FCSEL to decodetree

Commit Message

Richard Henderson May 24, 2024, 11:21 p.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/tcg/gengvec.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

Comments

Peter Maydell May 28, 2024, 3:59 p.m. UTC | #1

On Sat, 25 May 2024 at 00:29, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/tcg/gengvec.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM

diff mbox series

Patch

diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c
index 1d6bc6021d..1895c3b19f 100644
--- a/target/arm/tcg/gengvec.c
+++ b/target/arm/tcg/gengvec.c
@@ -943,9 +943,7 @@  void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
 
 static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
 {
-    tcg_gen_and_vec(vece, d, a, b);
-    tcg_gen_dupi_vec(vece, a, 0);
-    tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
+    tcg_gen_cmp_vec(TCG_COND_TSTNE, vece, d, a, b);
 }
 
 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,