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(cust-west-par-46-193-4-103.cust.wifirst.net [46.193.4.103]) by zproxy4.enst.fr (Postfix) with ESMTPSA id 036B9205A4; Sun, 17 Mar 2024 11:41:09 +0100 (CET) From: Arnaud Minier To: qemu-devel@nongnu.org Cc: Samuel Tardieu , =?utf-8?q?Marc-Andr?= =?utf-8?q?=C3=A9_Lureau?= , Alistair Francis , Paolo Bonzini , =?utf-8?q?In=C3=A8s_Varhol?= , Peter Maydell , qemu-arm@nongnu.org, Laurent Vivier , Thomas Huth , Arnaud Minier Subject: [PATCH 4/7] hw/char/stm32l4x5_usart: Enable serial read and write Date: Sun, 17 Mar 2024 11:39:15 +0100 Message-Id: <20240317103918.44375-5-arnaud.minier@telecom-paris.fr> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240317103918.44375-1-arnaud.minier@telecom-paris.fr> References: <20240317103918.44375-1-arnaud.minier@telecom-paris.fr> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:660:330f:2::df; envelope-from=arnaud.minier@telecom-paris.fr; helo=zproxy4.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the ability to read and write characters to the usart using the serial port. Signed-off-by: Arnaud Minier Signed-off-by: Inès Varhol --- hw/char/stm32l4x5_usart.c | 105 +++++++++++++++++++++++++++++++++++++- hw/char/trace-events | 1 + 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index f58bd56875..958d05a56d 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -154,6 +154,71 @@ REG32(RDR, 0x24) REG32(TDR, 0x28) FIELD(TDR, TDR, 0, 8) +static int stm32l4x5_usart_base_can_receive(void *opaque) +{ + Stm32l4x5UsartBaseState *s = opaque; + + if (!(s->isr & R_ISR_RXNE_MASK)) { + return 1; + } + + return 0; +} + +static void stm32l4x5_update_irq(Stm32l4x5UsartBaseState *s) +{ + if (((s->isr & R_ISR_WUF_MASK) && (s->cr3 & R_CR3_WUFIE_MASK)) || + ((s->isr & R_ISR_CMF_MASK) && (s->cr1 & R_CR1_CMIE_MASK)) || + ((s->isr & R_ISR_ABRF_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || + ((s->isr & R_ISR_EOBF_MASK) && (s->cr1 & R_CR1_EOBIE_MASK)) || + ((s->isr & R_ISR_RTOF_MASK) && (s->cr1 & R_CR1_RTOIE_MASK)) || + ((s->isr & R_ISR_CTSIF_MASK) && (s->cr3 & R_CR3_CTSIE_MASK)) || + ((s->isr & R_ISR_LBDF_MASK) && (s->cr2 & R_CR2_LBDIE_MASK)) || + ((s->isr & R_ISR_TXE_MASK) && (s->cr1 & R_CR1_TXEIE_MASK)) || + ((s->isr & R_ISR_TC_MASK) && (s->cr1 & R_CR1_TCIE_MASK)) || + ((s->isr & R_ISR_RXNE_MASK) && (s->cr1 & R_CR1_RXNEIE_MASK)) || + ((s->isr & R_ISR_IDLE_MASK) && (s->cr1 & R_CR1_IDLEIE_MASK)) || + ((s->isr & R_ISR_ORE_MASK) && + ((s->cr1 & R_CR1_RXNEIE_MASK) || (s->cr3 & R_CR3_EIE_MASK))) || + /* TODO: Handle NF ? */ + ((s->isr & R_ISR_FE_MASK) && (s->cr3 & R_CR3_EIE_MASK)) || + ((s->isr & R_ISR_PE_MASK) && (s->cr1 & R_CR1_PEIE_MASK))) { + qemu_irq_raise(s->irq); + trace_stm32l4x5_usart_irq_raised(s->isr); + } else { + qemu_irq_lower(s->irq); + trace_stm32l4x5_usart_irq_lowered(); + } +} + +static void stm32l4x5_usart_base_receive(void *opaque, const uint8_t *buf, int size) +{ + Stm32l4x5UsartBaseState *s = opaque; + + if (!((s->cr1 & R_CR1_UE_MASK) && (s->cr1 & R_CR1_RE_MASK))) { + /* USART not enabled - drop the chars */ + trace_stm32l4x5_usart_error("Dropping the chars\n"); + return; + } + + /* Check if overrun detection is enabled and if there is an overrun */ + if (!(s->cr3 & R_CR3_OVRDIS_MASK) && (s->isr & R_ISR_RXNE_MASK)) { + /* + * A character has been received while + * the previous has not been read = Overrun. + */ + s->isr |= R_ISR_ORE_MASK; + trace_stm32l4x5_usart_overrun_detected(s->rdr, *buf); + } else { + /* No overrun */ + s->rdr = *buf; + s->isr |= R_ISR_RXNE_MASK; + trace_stm32l4x5_usart_rx(s->rdr); + } + + stm32l4x5_update_irq(s); +} + static void stm32l4x5_usart_base_reset_hold(Object *obj) { Stm32l4x5UsartBaseState *s = STM32L4X5_USART_BASE(obj); @@ -168,6 +233,21 @@ static void stm32l4x5_usart_base_reset_hold(Object *obj) s->isr = 0x020000C0 | R_ISR_TXE_MASK; s->rdr = 0x00000000; s->tdr = 0x00000000; + + stm32l4x5_update_irq(s); +} + +static void usart_update_rqr(Stm32l4x5UsartBaseState *s, uint32_t value) +{ + /* TXFRQ */ + /* Reset RXNE flag */ + if (value & R_RQR_RXFRQ_MASK) { + s->isr &= ~R_ISR_RXNE_MASK; + } + /* MMRQ */ + /* SBKRQ */ + /* ABRRQ */ + stm32l4x5_update_irq(s); } static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, @@ -209,7 +289,8 @@ static uint64_t stm32l4x5_usart_base_read(void *opaque, hwaddr addr, case A_RDR: retvalue = FIELD_EX32(s->rdr, RDR, RDR); /* Reset RXNE flag */ - s->isr &= ~USART_ISR_RXNE; + s->isr &= ~R_ISR_RXNE_MASK; + stm32l4x5_update_irq(s); break; case A_TDR: retvalue = FIELD_EX32(s->tdr, TDR, TDR); @@ -237,6 +318,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, switch (addr) { case A_CR1: s->cr1 = value; + stm32l4x5_update_irq(s); return; case A_CR2: s->cr2 = value; @@ -254,6 +336,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, s->rtor = value; return; case A_RQR: + usart_update_rqr(s, value); return; case A_ISR: qemu_log_mask(LOG_GUEST_ERROR, @@ -262,6 +345,7 @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, case A_ICR: /* Clear the status flags */ s->isr &= ~value; + stm32l4x5_update_irq(s); return; case A_RDR: qemu_log_mask(LOG_GUEST_ERROR, @@ -269,6 +353,21 @@ static void stm32l4x5_usart_base_write(void *opaque, hwaddr addr, return; case A_TDR: s->tdr = value; + ch = value & R_TDR_TDR_MASK; + /* + * XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks + */ + qemu_chr_fe_write_all(&s->chr, &ch, 1); + /* + * XXX I/O are currently synchronous, making it impossible for + * software to observe transient states where TXE or TC aren't + * set. Unlike TXE however, which is read-only, software may + * clear TC by writing 0 to the ISR register, so set it again + * on each write. + */ + s->isr |= R_ISR_TC_MASK; + stm32l4x5_update_irq(s); return; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -338,6 +437,10 @@ static void stm32l4x5_usart_base_realize(DeviceState *dev, Error **errp) error_setg(errp, "USART clock must be wired up by SoC code"); return; } + + qemu_chr_fe_set_handlers(&s->chr, stm32l4x5_usart_base_can_receive, + stm32l4x5_usart_base_receive, NULL, NULL, + s, NULL, true); } static void stm32l4x5_usart_base_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/trace-events b/hw/char/trace-events index 9f5fda0eb8..0cda3dfed0 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -114,6 +114,7 @@ stm32l4x5_usart_rx(uint8_t c) "USART: got character 0x%x from backend" stm32l4x5_usart_tx(uint8_t c) "USART: character 0x%x sent to backend" stm32l4x5_usart_irq_raised(uint32_t reg) "USART: IRQ raised: 0x%08"PRIx32 stm32l4x5_usart_irq_lowered(void) "USART: IRQ lowered" +stm32l4x5_usart_overrun_detected(uint8_t current, uint8_t received) "USART: Overrun detected, RDR='0x%x', received 0x%x" stm32l4x5_usart_error(const char* error) "USART Error: %s" # xen_console.c