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Fri, 15 Mar 2024 06:10:00 -0700 (PDT) Received: from m1x-phil.lan ([176.176.145.26]) by smtp.gmail.com with ESMTPSA id q10-20020aa7d44a000000b005689d0a97d1sm1657891edr.24.2024.03.15.06.09.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 15 Mar 2024 06:10:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Markus Armbruster Cc: qemu-riscv@nongnu.org, Anton Johansson , qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, =?utf-8?q?Daniel_P_=2E_Berrang?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Eduardo Habkost , Claudio Fontana , Richard Henderson , Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , Manos Pitsidianakis , Zhao Liu , qemu-arm@nongnu.org, Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Huacai Chen Subject: [PATCH-for-9.1 07/21] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types Date: Fri, 15 Mar 2024 14:08:55 +0100 Message-ID: <20240315130910.15750-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240315130910.15750-1-philmd@linaro.org> References: <20240315130910.15750-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending on the mips(32)/mips64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types, both inheriting a common TYPE_MIPS_CPU base type. Keep the current CPU types registered in mips_register_cpudef_type() as 32 or 64-bit, but instead of depending on the binary built being targeting 32/64-bit, check whether the CPU is 64-bit by looking at the CPU_MIPS64 bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu-qom.h | 13 +++++++------ target/mips/cpu.c | 11 ++++++++++- target/mips/sysemu/mips-qmp-cmds.c | 26 ++------------------------ 3 files changed, 19 insertions(+), 31 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 0eea2a2598..bf464f16b6 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MIPS CPU + * QEMU MIPS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -22,14 +22,15 @@ #include "hw/core/cpu.h" -#ifdef TARGET_MIPS64 -#define TYPE_MIPS_CPU "mips64-cpu" -#else -#define TYPE_MIPS_CPU "mips-cpu" -#endif +#define TYPE_MIPS_CPU "mips-cpu" +#define TYPE_MIPS32_CPU "mips32-cpu" +#define TYPE_MIPS64_CPU "mips64-cpu" OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) + #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX diff --git a/target/mips/cpu.c b/target/mips/cpu.c index c096d97fe3..f3ea6175f2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -604,6 +604,14 @@ static const TypeInfo mips_cpu_types[] = { .abstract = true, .class_size = sizeof(MIPSCPUClass), .class_init = mips_cpu_class_init, + }, { + .name = TYPE_MIPS32_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, + }, { + .name = TYPE_MIPS64_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, } }; @@ -620,7 +628,8 @@ static void mips_register_cpudef_type(const struct mips_def_t *def) char *typename = mips_cpu_type_name(def->name); TypeInfo ti = { .name = typename, - .parent = TYPE_MIPS_CPU, + .parent = def->insn_flags & CPU_MIPS64 + ? TYPE_MIPS64_CPU : TYPE_MIPS32_CPU, .class_init = mips_cpu_cpudef_class_init, .class_data = (void *)def, }; diff --git a/target/mips/sysemu/mips-qmp-cmds.c b/target/mips/sysemu/mips-qmp-cmds.c index 7340ac70ba..329db3a028 100644 --- a/target/mips/sysemu/mips-qmp-cmds.c +++ b/target/mips/sysemu/mips-qmp-cmds.c @@ -8,31 +8,9 @@ #include "qemu/osdep.h" #include "qapi/qapi-commands-machine-target.h" -#include "cpu.h" - -static void mips_cpu_add_definition(gpointer data, gpointer user_data) -{ - ObjectClass *oc = data; - CpuDefinitionInfoList **cpu_list = user_data; - CpuDefinitionInfo *info; - const char *typename; - - typename = object_class_get_name(oc); - info = g_malloc0(sizeof(*info)); - info->name = cpu_model_from_type(typename); - info->q_typename = g_strdup(typename); - - QAPI_LIST_PREPEND(*cpu_list, info); -} +#include "qapi/commands-target-compat.h" CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { - CpuDefinitionInfoList *cpu_list = NULL; - GSList *list; - - list = object_class_get_list(TYPE_MIPS_CPU, false); - g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); - g_slist_free(list); - - return cpu_list; + return generic_query_cpu_definitions(errp); }