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Mon, 19 Feb 2024 00:30:55 -0800 (PST) Received: from wheely.local0.net ([1.146.38.93]) by smtp.gmail.com with ESMTPSA id mo7-20020a1709030a8700b001db5ecd115bsm3838348plb.276.2024.02.19.00.30.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Feb 2024 00:30:55 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-ppc@nongnu.org, Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , Harsh Prateek Bora Subject: [PULL 12/49] target/ppc: Rename registers to match ISA Date: Mon, 19 Feb 2024 18:29:01 +1000 Message-ID: <20240219082938.238302-13-npiggin@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240219082938.238302-1-npiggin@gmail.com> References: <20240219082938.238302-1-npiggin@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Several registers have names that don't match the ISA (or convention with other QEMU PPC registers), making them unintuitive to use with GDB. Fortunately most of these registers are obscure and/or have not been correctly implemented in the gdb server (e.g., DEC, TB, CFAR), so risk of breaking users should be low. QEMU should follow the ISA for register name convention (where there is no established GDB name). Acked-by: Cédric Le Goater Signed-off-by: Nicholas Piggin --- target/ppc/cpu_init.c | 20 ++++++++++---------- target/ppc/helper_regs.c | 2 +- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9931372a08..9bccddb350 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5062,7 +5062,7 @@ static void register_970_hid_sprs(CPUPPCState *env) static void register_970_hior_sprs(CPUPPCState *env) { - spr_register(env, SPR_HIOR, "SPR_HIOR", + spr_register(env, SPR_HIOR, "HIOR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_hior, &spr_write_hior, 0x00000000); @@ -5070,11 +5070,11 @@ static void register_970_hior_sprs(CPUPPCState *env) static void register_book3s_ctrl_sprs(CPUPPCState *env) { - spr_register(env, SPR_CTRL, "SPR_CTRL", + spr_register(env, SPR_CTRL, "CTRL", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, &spr_write_CTRL, 0x00000000); - spr_register(env, SPR_UCTRL, "SPR_UCTRL", + spr_register(env, SPR_UCTRL, "UCTRL", &spr_read_ureg, SPR_NOACCESS, &spr_read_ureg, SPR_NOACCESS, 0x00000000); @@ -5465,7 +5465,7 @@ static void register_book3s_purr_sprs(CPUPPCState *env) static void register_power6_dbg_sprs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) - spr_register(env, SPR_CFAR, "SPR_CFAR", + spr_register(env, SPR_CFAR, "CFAR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_cfar, &spr_write_cfar, 0x00000000); @@ -5483,7 +5483,7 @@ static void register_power5p_common_sprs(CPUPPCState *env) static void register_power6_common_sprs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) - spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", + spr_register_kvm(env, SPR_DSCR, "DSCR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DSCR, 0x00000000); @@ -5695,7 +5695,7 @@ static void register_power8_book4_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic, KVM_REG_PPC_ACOP, 0); /* PID is only in BookE in ISA v2.07 */ - spr_register_kvm(env, SPR_BOOKS_PID, "PID", + spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_pidr, KVM_REG_PPC_PID, 0); @@ -5716,7 +5716,7 @@ static void register_power7_book4_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic, KVM_REG_PPC_ACOP, 0); /* PID is only in BookE in ISA v2.06 */ - spr_register_kvm(env, SPR_BOOKS_PID, "PID", + spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic32, KVM_REG_PPC_PID, 0); @@ -5750,7 +5750,7 @@ static void register_power9_mmu_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic, 0x0000000000000000); /* PID is part of the BookS ISA from v3.0 */ - spr_register_kvm(env, SPR_BOOKS_PID, "PID", + spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_pidr, KVM_REG_PPC_PID, 0); @@ -5791,7 +5791,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic32, 0); - spr_register(env, SPR_UDEXCR, "DEXCR", + spr_register(env, SPR_UDEXCR, "UDEXCR", &spr_read_dexcr_ureg, SPR_NOACCESS, &spr_read_dexcr_ureg, SPR_NOACCESS, 0); @@ -5802,7 +5802,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic32, 0); - spr_register(env, SPR_UHDEXCR, "HDEXCR", + spr_register(env, SPR_UHDEXCR, "UHDEXCR", &spr_read_dexcr_ureg, SPR_NOACCESS, &spr_read_dexcr_ureg, SPR_NOACCESS, 0); diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index e0b2dcd02e..8324ff22db 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -490,7 +490,7 @@ void register_non_embedded_sprs(CPUPPCState *env) &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DAR, 0x00000000); /* Timer */ - spr_register(env, SPR_DECR, "DECR", + spr_register(env, SPR_DECR, "DEC", SPR_NOACCESS, SPR_NOACCESS, &spr_read_decr, &spr_write_decr, 0x00000000);