| Message ID | 20240119112129.20067-2-rbradford@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Add support for Zaamo & Zalrsc | expand |
On Fri, Jan 19, 2024 at 9:22 PM Rob Bradford <rbradford@rivosinc.com> wrote: > > These extensions represent the atomic operations from A (Zaamo) and the > Load-Reserved/Store-Conditional operations from A (Zalrsc) > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com> > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu_cfg.h | 2 ++ > 2 files changed, 7 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8d3ec74a1c..604baf53c8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -103,7 +103,9 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > + ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), > ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), > + ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), > ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), > @@ -1491,6 +1493,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), > > + MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false), > + MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false), We should implement the extension before we expose it to userspace. That helps maintain bisectability of the code Alistair > + > MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false), > MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false), > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index fea14c275f..cc4c30244c 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -78,7 +78,9 @@ struct RISCVCPUConfig { > bool ext_svnapot; > bool ext_svpbmt; > bool ext_zdinx; > + bool ext_zaamo; > bool ext_zacas; > + bool ext_zalrsc; > bool ext_zawrs; > bool ext_zfa; > bool ext_zfbfmin; > -- > 2.43.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8d3ec74a1c..604baf53c8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -103,7 +103,9 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), + ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo), ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas), + ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), @@ -1491,6 +1493,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), + MULTI_EXT_CFG_BOOL("x-zaamo", ext_zaamo, false), + MULTI_EXT_CFG_BOOL("x-zalrsc", ext_zalrsc, false), + MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false), MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index fea14c275f..cc4c30244c 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,7 +78,9 @@ struct RISCVCPUConfig { bool ext_svnapot; bool ext_svpbmt; bool ext_zdinx; + bool ext_zaamo; bool ext_zacas; + bool ext_zalrsc; bool ext_zawrs; bool ext_zfa; bool ext_zfbfmin;