diff mbox series

[10/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()

Message ID 20240112213812.173521-11-dbarboza@ventanamicro.com
State New
Headers show
Series target/riscv: add 'cpu->cfg.vlenb', remove 'cpu->cfg.vlen' | expand

Commit Message

Daniel Henrique Barboza Jan. 12, 2024, 9:38 p.m. UTC
MAXSZ() returns the value in bytes. Now that we have access to vlenb
we don't need to compensate with a '-3' in the scale to use 'vlen'.

MAXSZ() now works as follows:

LMUL  lmul=scale  MAXSZ (vlenb >> -scale)
  1       0       vlenb
  2       1       vlenb << 1
  4       2       vlenb << 2
  8       3       vlenb << 3
1/8      -3       vlenb >> 3
1/4      -2       vlenb >> 2
1/2      -1       vlenb >> 1

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

Comments

Richard Henderson Jan. 12, 2024, 10:45 p.m. UTC | #1
On 1/13/24 08:38, Daniel Henrique Barboza wrote:
> MAXSZ() returns the value in bytes. Now that we have access to vlenb
> we don't need to compensate with a '-3' in the scale to use 'vlen'.
> 
> MAXSZ() now works as follows:
> 
> LMUL  lmul=scale  MAXSZ (vlenb >> -scale)
>    1       0       vlenb
>    2       1       vlenb << 1
>    4       2       vlenb << 2
>    8       3       vlenb << 3

Um, what?

>   static inline uint32_t MAXSZ(DisasContext *s)
>   {
> -    int scale = s->lmul - 3;
> -    return s->cfg_ptr->vlen >> -scale;
> +    return s->cfg_ptr->vlenb >> -s->lmul;

There's no left-shift here, either before or after.
Bug?


r~
Daniel Henrique Barboza Jan. 15, 2024, 1:51 p.m. UTC | #2
On 1/12/24 19:45, Richard Henderson wrote:
> On 1/13/24 08:38, Daniel Henrique Barboza wrote:
>> MAXSZ() returns the value in bytes. Now that we have access to vlenb
>> we don't need to compensate with a '-3' in the scale to use 'vlen'.
>>
>> MAXSZ() now works as follows:
>>
>> LMUL  lmul=scale  MAXSZ (vlenb >> -scale)
>>    1       0       vlenb
>>    2       1       vlenb << 1
>>    4       2       vlenb << 2
>>    8       3       vlenb << 3
> 
> Um, what?
> 
>>   static inline uint32_t MAXSZ(DisasContext *s)
>>   {
>> -    int scale = s->lmul - 3;
>> -    return s->cfg_ptr->vlen >> -scale;
>> +    return s->cfg_ptr->vlenb >> -s->lmul;
> 
> There's no left-shift here, either before or after.
> Bug?

Yeah, I got lost in that explanation. I'll simplify it to be just a simple case of
adjusting the right shift to use vlenb like in patches 8 and 9.


Thanks,


Daniel



> 
> 
> r~
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d743675262..804cfd6c7f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1160,12 +1160,11 @@  GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
 /*
  * MAXSZ returns the maximum vector size can be operated in bytes,
  * which is used in GVEC IR when vl_eq_vlmax flag is set to true
- * to accerlate vector operation.
+ * to accelerate vector operation.
  */
 static inline uint32_t MAXSZ(DisasContext *s)
 {
-    int scale = s->lmul - 3;
-    return s->cfg_ptr->vlen >> -scale;
+    return s->cfg_ptr->vlenb >> -s->lmul;
 }
 
 static bool opivv_check(DisasContext *s, arg_rmrr *a)