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[v2,3/3] target/i386/cpu: Fix typo in comment

Message ID 20240106132546.21248-4-shentey@gmail.com
State New
Headers show
Series Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled | expand

Commit Message

Bernhard Beschow Jan. 6, 2024, 1:25 p.m. UTC
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
 target/i386/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2524881ce2..7d11edf4fa 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2178,7 +2178,7 @@  static const CPUCaches epyc_genoa_cache_info = {
  *  Conceal VM entries from PT
  *  Enable ENCLS exiting
  *  Mode-based execute control (XS/XU)
- s  TSC scaling (Skylake Server and newer)
+ *  TSC scaling (Skylake Server and newer)
  *  GPA translation for PT (IceLake and newer)
  *  User wait and pause
  *  ENCLV exiting