diff mbox series

[v3,5/6] target/riscv: Update address modify functions to take into account pointer masking

Message ID 20240103185716.1790546-6-me@deliversmonkey.space
State New
Headers show
Series Pointer Masking update for Zjpm v0.8 | expand

Commit Message

Alexey Baturo Jan. 3, 2024, 6:57 p.m. UTC 
From: Alexey Baturo <baturo.alexey@gmail.com>

Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
 target/riscv/translate.c     | 12 ++++++++----
 target/riscv/vector_helper.c | 12 ++++++++++++
 2 files changed, 20 insertions(+), 4 deletions(-)

Comments

Richard Henderson Jan. 3, 2024, 10:18 p.m. UTC | #1 
On 1/4/24 05:57, Alexey Baturo wrote:
> From: Alexey Baturo <baturo.alexey@gmail.com>
> 
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
>   target/riscv/translate.c     | 12 ++++++++----
>   target/riscv/vector_helper.c | 12 ++++++++++++
>   2 files changed, 20 insertions(+), 4 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
Deepak Gupta Jan. 5, 2024, 1:02 a.m. UTC | #2 
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
>
>  static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
>  {
> +    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> +    if (pmm == PMM_FIELD_DISABLED)
> +        return addr;
> +    int pmlen = riscv_pm_get_pmlen(pmm);
> +    bool signext = !riscv_cpu_bare_mode(env);
> +    addr = addr << pmlen;
> +    /* sign/zero extend masked address by N-1 bit */
> +    if (signext) {
> +        addr = (target_long)addr >> pmlen;

These look like right shift operations and not sign extensions of N-1 bit

> +    } else {
> +        addr = addr >> pmlen;

Same here.

> +    }
>      return addr;
>  }
>
> --
> 2.34.1
>
>
Alexey Baturo Jan. 5, 2024, 7:29 a.m. UTC | #3 
> +    addr = addr << pmlen;
> +    if (signext) {
> +        addr = (target_long)addr >> pmlen;
> +    } else {
> +        addr = addr >> pmlen;
Could you please elaborate a bit more on your concern here?
I believe this code works as intended: https://godbolt.org/z/b9c7na13a

Thanks

пт, 5 янв. 2024 г. в 04:02, Deepak Gupta <debug@rivosinc.com>:

> > --- a/target/riscv/vector_helper.c
> > +++ b/target/riscv/vector_helper.c
> > @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc,
> uint32_t log2_esz)
> >
> >  static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong
> addr)
> >  {
> > +    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> > +    if (pmm == PMM_FIELD_DISABLED)
> > +        return addr;
> > +    int pmlen = riscv_pm_get_pmlen(pmm);
> > +    bool signext = !riscv_cpu_bare_mode(env);
> > +    addr = addr << pmlen;
> > +    /* sign/zero extend masked address by N-1 bit */
> > +    if (signext) {
> > +        addr = (target_long)addr >> pmlen;
>
> These look like right shift operations and not sign extensions of N-1 bit
>
> > +    } else {
> > +        addr = addr >> pmlen;
>
> Same here.
>
> > +    }
> >      return addr;
> >  }
> >
> > --
> > 2.34.1
> >
> >
>
Deepak Gupta Jan. 5, 2024, 6:07 p.m. UTC | #4 
On Fri, Jan 05, 2024 at 10:29:35AM +0300, Alexey Baturo wrote:
>> +    addr = addr << pmlen;
>> +    if (signext) {
>> +        addr = (target_long)addr >> pmlen;
>> +    } else {
>> +        addr = addr >> pmlen;
>Could you please elaborate a bit more on your concern here?
>I believe this code works as intended: https://godbolt.org/z/b9c7na13a
Nevermind I missed this above in code.
addr = addr << pmlen;

You're good. Sorry about that.
>
>Thanks
>
>пт, 5 янв. 2024 г. в 04:02, Deepak Gupta <debug@rivosinc.com>:
>
>> > --- a/target/riscv/vector_helper.c
>> > +++ b/target/riscv/vector_helper.c
>> > @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc,
>> uint32_t log2_esz)
>> >
>> >  static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong
>> addr)
>> >  {
>> > +    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
>> > +    if (pmm == PMM_FIELD_DISABLED)
>> > +        return addr;
>> > +    int pmlen = riscv_pm_get_pmlen(pmm);
>> > +    bool signext = !riscv_cpu_bare_mode(env);
>> > +    addr = addr << pmlen;
>> > +    /* sign/zero extend masked address by N-1 bit */
>> > +    if (signext) {
>> > +        addr = (target_long)addr >> pmlen;
>>
>> These look like right shift operations and not sign extensions of N-1 bit
>>
>> > +    } else {
>> > +        addr = addr >> pmlen;
>>
>> Same here.
>>
>> > +    }
>> >      return addr;
>> >  }
>> >
>> > --
>> > 2.34.1
>> >
>> >
>>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8ac2819fa5..457de381c7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -579,8 +579,10 @@  static TCGv get_address(DisasContext *ctx, int rs1, int imm)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_addi_tl(addr, src1, imm);
-    if (get_address_xl(ctx) == MXL_RV32) {
-        tcg_gen_ext32u_tl(addr, addr);
+    if (ctx->addr_signed) {
+        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
+    } else {
+        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
     }
 
     return addr;
@@ -593,8 +595,10 @@  static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
 
     tcg_gen_add_tl(addr, src1, offs);
-    if (get_xl(ctx) == MXL_RV32) {
-        tcg_gen_ext32u_tl(addr, addr);
+    if (ctx->addr_signed) {
+        tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
+    } else {
+        tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
     }
     return addr;
 }
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8e7a8e80a0..b91c21d1f4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -94,6 +94,18 @@  static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
 
 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
 {
+    RISCVPmPmm pmm = riscv_pm_get_pmm(env);
+    if (pmm == PMM_FIELD_DISABLED)
+        return addr;
+    int pmlen = riscv_pm_get_pmlen(pmm);
+    bool signext = !riscv_cpu_bare_mode(env);
+    addr = addr << pmlen;
+    /* sign/zero extend masked address by N-1 bit */
+    if (signext) {
+        addr = (target_long)addr >> pmlen;
+    } else {
+        addr = addr >> pmlen;
+    }
     return addr;
 }