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[PULL,23/27] target/riscv/cpu.h: spelling fix: separatly

Message ID 20231116074441.3202417-24-mjt@tls.msk.ru
State New
Headers show
Series [PULL,01/27] hw/watchdog/wdt_aspeed: Remove unused 'hw/misc/aspeed_scu.h' header | expand

Commit Message

Michael Tokarev Nov. 16, 2023, 7:44 a.m. UTC 
Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ filtering support."
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---
 target/riscv/cpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf58b0f0b5..d74b361be6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -214,13 +214,13 @@  struct CPUArchState {
 
     /*
      * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
-     * alias of mie[i] and needs to be maintained separatly.
+     * alias of mie[i] and needs to be maintained separately.
      */
     uint64_t sie;
 
     /*
      * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
-     * alias of sie[i] (mie[i]) and needs to be maintained separatly.
+     * alias of sie[i] (mie[i]) and needs to be maintained separately.
      */
     uint64_t vsie;