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[2/2] hw/pci-host: Designware: Add outbound iATU no address match behavior

Message ID 20231115143341.13068-3-max.hsu@sifive.com
State New
Headers show
Series hw/pci-host: Fix Designware no address match behavior | expand

Commit Message

Max Hsu Nov. 15, 2023, 2:33 p.m. UTC 
IMX6DQRM Rev4, in chapter 48.3.9.2, specifies for outbound iATU with
no address match: 'If there is no address match, then the address is
untranslated.'
The current model implementation only considers inbound occurrences,
neglecting outbound scenarios.

To address this, we introduce a new MemoryRegion to handle the behavior
of no address match in outbound transactions.

This fix has been tested with the integration of Designware PCIe RC
along with the e1000e Ethernet card, ensuring proper functioning of
network transmissions and MSI interrupts.

Signed-off-by: Max Hsu <max.hsu@sifive.com>
---
 hw/pci-host/designware.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 83dd9b1aaf..d0be8dec68 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -499,6 +499,7 @@  static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
      * to have the lowest priority.
      */
     MemoryRegion *inbound_untranslated = g_new(MemoryRegion, 1);
+    MemoryRegion *outbound_untranslated = g_new(MemoryRegion, 1);
 
     memory_region_init_alias(inbound_untranslated, OBJECT(root),
                              "inbound untranslated pass",
@@ -510,6 +511,16 @@  static void designware_pcie_root_realize(PCIDevice *dev, Error **errp)
     memory_region_set_address(inbound_untranslated, 0x0ULL);
     memory_region_set_enabled(inbound_untranslated, true);
 
+    memory_region_init_alias(outbound_untranslated, OBJECT(root),
+                             "outbound untranslated pass",
+                             &host->pci.memory, dummy_offset, dummy_size);
+    memory_region_add_subregion_overlap(get_system_memory(),
+                                        dummy_offset, outbound_untranslated,
+                                        INT32_MIN);
+    memory_region_set_size(outbound_untranslated, UINT64_MAX);
+    memory_region_set_address(outbound_untranslated, 0x0ULL);
+    memory_region_set_enabled(outbound_untranslated, true);
+
     memory_region_init_io(&root->msi.iomem, OBJECT(root),
                           &designware_pci_host_msi_ops,
                           root, "pcie-msi", 0x4);