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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id ja20-20020a170902efd400b001c1f4edfb9csm726348plb.173.2023.10.11.21.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 21:12:06 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , Andrew Jones Subject: [PULL 18/54] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Date: Thu, 12 Oct 2023 14:10:15 +1000 Message-ID: <20231012041051.2572507-19-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012041051.2572507-1-alistair.francis@wdc.com> References: <20231012041051.2572507-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Daniel Henrique Barboza Before adding support to detect if an extension was user set we need to handle how we're enabling extensions in riscv_init_max_cpu_extensions(). object_property_set_bool() calls the set() callback for the property, and we're going to use this callback to set the 'multi_ext_user_opts' hash. This means that, as is today, all extensions we're setting for the 'max' CPU will be seen as user set in the future. Let's change set_bool() to isa_ext_update_enabled() that will just enable/disable the flag on a certain offset. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-ID: <20230912132423.268494-19-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fba5ce7118..821006f42a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2166,24 +2166,24 @@ static void riscv_init_max_cpu_extensions(Object *obj) set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { - object_property_set_bool(obj, prop->name, true, NULL); + isa_ext_update_enabled(cpu, prop->offset, true); } /* set vector version */ env->vext_ver = VEXT_VERSION_1_00_0; /* Zfinx is not compatible with F. Disable it */ - object_property_set_bool(obj, "zfinx", false, NULL); - object_property_set_bool(obj, "zdinx", false, NULL); - object_property_set_bool(obj, "zhinx", false, NULL); - object_property_set_bool(obj, "zhinxmin", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); - object_property_set_bool(obj, "zce", false, NULL); - object_property_set_bool(obj, "zcmp", false, NULL); - object_property_set_bool(obj, "zcmt", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); if (env->misa_mxl != MXL_RV32) { - object_property_set_bool(obj, "zcf", false, NULL); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); } }