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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id j26-20020aa783da000000b00687a4b70d1esm3577320pfn.218.2023.09.15.20.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 20:30:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 26/39] accel/tcg: Use CPUTLBEntryFull.phys_addr in io_failed Date: Fri, 15 Sep 2023 20:29:58 -0700 Message-Id: <20230916033011.479144-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916033011.479144-1-richard.henderson@linaro.org> References: <20230916033011.479144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since the introduction of CPUTLBEntryFull, we can recover the full cpu address space physical address without having to examine the MemoryRegionSection. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ae4ad591fe..a46be6a120 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1388,13 +1388,9 @@ io_prepare(hwaddr *out_offset, CPUArchState *env, hwaddr xlat, static void io_failed(CPUArchState *env, CPUTLBEntryFull *full, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, - MemTxResult response, uintptr_t retaddr, - MemoryRegionSection *section, hwaddr mr_offset) + MemTxResult response, uintptr_t retaddr) { - hwaddr physaddr = (mr_offset + - section->offset_within_address_space - - section->offset_within_region); - + hwaddr physaddr = full->phys_addr | (addr & ~TARGET_PAGE_MASK); cpu_transaction_failed(env_cpu(env), physaddr, addr, size, access_type, mmu_idx, full->attrs, response, retaddr); } @@ -1420,7 +1416,7 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, if (r != MEMTX_OK) { io_failed(env, full, addr, memop_size(op), access_type, mmu_idx, - r, retaddr, section, mr_offset); + r, retaddr); } return val; } @@ -1445,7 +1441,7 @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, if (r != MEMTX_OK) { io_failed(env, full, addr, memop_size(op), MMU_DATA_STORE, mmu_idx, - r, retaddr, section, mr_offset); + r, retaddr); } }