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[PULL,1/7] target/s390x: Define TARGET_HAS_PRECISE_SMC

Message ID 20230831191719.140001-2-thuth@redhat.com
State New
Headers show
Series [PULL,1/7] target/s390x: Define TARGET_HAS_PRECISE_SMC | expand

Commit Message

Thomas Huth Aug. 31, 2023, 7:17 p.m. UTC 
From: Ilya Leoshkevich <iii@linux.ibm.com>

PoP (Sequence of Storage References -> Instruction Fetching) says:

    ... if a store that is conceptually earlier is
    made by the same CPU using the same effective
    address as that by which the instruction is subse-
    quently fetched, the updated information is obtained ...

QEMU already has support for this in the common code; enable it for
s390x.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20230807114921.438881-1-iii@linux.ibm.com>
Acked-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
 target/s390x/cpu.h | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index eb5b65b7d3..304029e57c 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -36,6 +36,8 @@ 
 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */
 #define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL & ~TCG_MO_ST_LD)
 
+#define TARGET_HAS_PRECISE_SMC
+
 #define TARGET_INSN_START_EXTRA_WORDS 2
 
 #define MMU_USER_IDX 0