diff mbox series

[v4,35/48] target/loongarch: Implement xvpcnt

Message ID 20230830084902.2113960-36-gaosong@loongson.cn
State New
Headers show
Series Add LoongArch LASX instructions | expand

Commit Message

gaosong Aug. 30, 2023, 8:48 a.m. UTC 
This patch includes:
- VPCNT.{B/H/W/D}.

Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/insns.decode                | 5 +++++
 target/loongarch/disas.c                     | 5 +++++
 target/loongarch/vec_helper.c                | 4 ++--
 target/loongarch/insn_trans/trans_lasx.c.inc | 5 +++++
 4 files changed, 17 insertions(+), 2 deletions(-)

Comments

Richard Henderson Aug. 30, 2023, 11:28 p.m. UTC | #1 
On 8/30/23 01:48, Song Gao wrote:
> This patch includes:
> - VPCNT.{B/H/W/D}.
> 
> Signed-off-by: Song Gao<gaosong@loongson.cn>
> ---
>   target/loongarch/insns.decode                | 5 +++++
>   target/loongarch/disas.c                     | 5 +++++
>   target/loongarch/vec_helper.c                | 4 ++--
>   target/loongarch/insn_trans/trans_lasx.c.inc | 5 +++++
>   4 files changed, 17 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 3175532045..d683c6a6ab 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1779,6 +1779,11 @@  xvclz_h          0111 01101001 11000 00101 ..... .....    @vv
 xvclz_w          0111 01101001 11000 00110 ..... .....    @vv
 xvclz_d          0111 01101001 11000 00111 ..... .....    @vv
 
+xvpcnt_b         0111 01101001 11000 01000 ..... .....    @vv
+xvpcnt_h         0111 01101001 11000 01001 ..... .....    @vv
+xvpcnt_w         0111 01101001 11000 01010 ..... .....    @vv
+xvpcnt_d         0111 01101001 11000 01011 ..... .....    @vv
+
 xvreplgr2vr_b    0111 01101001 11110 00000 ..... .....    @vr
 xvreplgr2vr_h    0111 01101001 11110 00001 ..... .....    @vr
 xvreplgr2vr_w    0111 01101001 11110 00010 ..... .....    @vr
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 0fc58735b9..9e31f9bbbc 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2205,6 +2205,11 @@  INSN_LASX(xvclz_h,           vv)
 INSN_LASX(xvclz_w,           vv)
 INSN_LASX(xvclz_d,           vv)
 
+INSN_LASX(xvpcnt_b,          vv)
+INSN_LASX(xvpcnt_h,          vv)
+INSN_LASX(xvpcnt_w,          vv)
+INSN_LASX(xvpcnt_d,          vv)
+
 INSN_LASX(xvreplgr2vr_b,     vr)
 INSN_LASX(xvreplgr2vr_h,     vr)
 INSN_LASX(xvreplgr2vr_w,     vr)
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c
index 789f6b303e..9c2b52fd7d 100644
--- a/target/loongarch/vec_helper.c
+++ b/target/loongarch/vec_helper.c
@@ -2183,9 +2183,9 @@  void HELPER(NAME)(void *vd, void *vj, uint32_t desc) \
     int i;                                           \
     VReg *Vd = (VReg *)vd;                           \
     VReg *Vj = (VReg *)vj;                           \
+    int oprsz = simd_oprsz(desc);                    \
                                                      \
-    for (i = 0; i < LSX_LEN/BIT; i++)                \
-    {                                                \
+    for (i = 0; i < oprsz / (BIT / 8); i++) {        \
         Vd->E(i) = FN(Vj->E(i));                     \
     }                                                \
 }
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc b/target/loongarch/insn_trans/trans_lasx.c.inc
index 4227fbe629..2a24de178d 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -528,6 +528,11 @@  TRANS(xvclz_h, LASX, gen_vv, 32, gen_helper_vclz_h)
 TRANS(xvclz_w, LASX, gen_vv, 32, gen_helper_vclz_w)
 TRANS(xvclz_d, LASX, gen_vv, 32, gen_helper_vclz_d)
 
+TRANS(xvpcnt_b, LASX, gen_vv, 32, gen_helper_vpcnt_b)
+TRANS(xvpcnt_h, LASX, gen_vv, 32, gen_helper_vpcnt_h)
+TRANS(xvpcnt_w, LASX, gen_vv, 32, gen_helper_vpcnt_w)
+TRANS(xvpcnt_d, LASX, gen_vv, 32, gen_helper_vpcnt_d)
+
 TRANS(xvreplgr2vr_b, LASX, gvec_dup, 32, MO_8)
 TRANS(xvreplgr2vr_h, LASX, gvec_dup, 32, MO_16)
 TRANS(xvreplgr2vr_w, LASX, gvec_dup, 32, MO_32)