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([179.93.21.19]) by smtp.gmail.com with ESMTPSA id ds23-20020a0568705b1700b001c50fb56845sm966189oab.16.2023.08.25.06.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Aug 2023 06:09:17 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 06/20] target/riscv: add 'max_features' CPU flag Date: Fri, 25 Aug 2023 10:08:39 -0300 Message-ID: <20230825130853.511782-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230825130853.511782-1-dbarboza@ventanamicro.com> References: <20230825130853.511782-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The 'max' CPU type is being configured during init() time by enabling all relevant extensions. Instead of checking for 'max' CPU to enable all extensions, add a new CPU cfg flag 'max_features' that can be used by any CPU during its cpu_init() function. We'll check for it during post_init() time to decide whether we should enable the maximum amount of features in the current CPU instance. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e2e8724dc2..c35d58c64b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -424,6 +424,8 @@ static void riscv_max_cpu_init(Object *obj) CPURISCVState *env = &cpu->env; RISCVMXL mlx = MXL_RV64; + cpu->cfg.max_features = true; + #ifdef TARGET_RISCV32 mlx = MXL_RV32; #endif diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e6a0f245c..df723e697b 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -137,6 +137,7 @@ struct RISCVCPUConfig { bool epmp; bool debug; bool misa_w; + bool max_features; bool short_isa_string;