| Message ID | 20230825121651.1534-3-zhiwei_liu@linux.alibaba.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add API for list cpu extensions | expand |
On 8/25/23 09:16, LIU Zhiwei wrote: > This API used for output current configuration for one specified CPU. > Currently only RISC-V frontend implements this API. > > Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> > --- > cpu.c | 8 ++++++++ > include/exec/cpu-common.h | 1 + > target/riscv/cpu.c | 10 ++++++++++ > target/riscv/cpu.h | 2 ++ > 4 files changed, 21 insertions(+) > > diff --git a/cpu.c b/cpu.c > index e1a9239d0f..03a313cd72 100644 > --- a/cpu.c > +++ b/cpu.c > @@ -299,6 +299,14 @@ void list_cpus(void) > #endif > } > > +void list_cpu_props(CPUState *cs) > +{ > + /* XXX: implement xxx_cpu_list_props for targets that still miss it */ > +#if defined(cpu_list_props) > + cpu_list_props(cs); > +#endif > +} > + > #if defined(CONFIG_USER_ONLY) > void tb_invalidate_phys_addr(hwaddr addr) > { > diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h > index 87dc9a752c..b3160d9218 100644 > --- a/include/exec/cpu-common.h > +++ b/include/exec/cpu-common.h > @@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, > > /* vl.c */ > void list_cpus(void); > +void list_cpu_props(CPUState *); > > #endif /* CPU_COMMON_H */ > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6b93b04453..3ea18de06f 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2226,6 +2226,16 @@ void riscv_cpu_list(void) > g_slist_free(list); > } > > +void riscv_cpu_list_props(CPUState *cs) > +{ > + char *enabled_isa; > + > + enabled_isa = riscv_isa_string(RISCV_CPU(cs)); > + qemu_printf("Enable extension:\n"); I suggest "Enabled extensions". LGTM otherwise. Daniel > + qemu_printf("\t%s\n", enabled_isa); > + /* TODO: output all user configurable options and all possible extensions */ > +} > + > #define DEFINE_CPU(type_name, initfn) \ > { \ > .name = type_name, \ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6ea22e0eea..af1d47605b 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > bool probe, uintptr_t retaddr); > char *riscv_isa_string(RISCVCPU *cpu); > void riscv_cpu_list(void); > +void riscv_cpu_list_props(CPUState *cs); > void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); > > #define cpu_list riscv_cpu_list > +#define cpu_list_props riscv_cpu_list_props > #define cpu_mmu_index riscv_cpu_mmu_index > > #ifndef CONFIG_USER_ONLY
On 2023/8/25 21:46, Daniel Henrique Barboza wrote: > > > On 8/25/23 09:16, LIU Zhiwei wrote: >> This API used for output current configuration for one specified CPU. >> Currently only RISC-V frontend implements this API. >> >> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> >> --- >> cpu.c | 8 ++++++++ >> include/exec/cpu-common.h | 1 + >> target/riscv/cpu.c | 10 ++++++++++ >> target/riscv/cpu.h | 2 ++ >> 4 files changed, 21 insertions(+) >> >> diff --git a/cpu.c b/cpu.c >> index e1a9239d0f..03a313cd72 100644 >> --- a/cpu.c >> +++ b/cpu.c >> @@ -299,6 +299,14 @@ void list_cpus(void) >> #endif >> } >> +void list_cpu_props(CPUState *cs) >> +{ >> + /* XXX: implement xxx_cpu_list_props for targets that still miss >> it */ >> +#if defined(cpu_list_props) >> + cpu_list_props(cs); >> +#endif >> +} >> + >> #if defined(CONFIG_USER_ONLY) >> void tb_invalidate_phys_addr(hwaddr addr) >> { >> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h >> index 87dc9a752c..b3160d9218 100644 >> --- a/include/exec/cpu-common.h >> +++ b/include/exec/cpu-common.h >> @@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, >> /* vl.c */ >> void list_cpus(void); >> +void list_cpu_props(CPUState *); >> #endif /* CPU_COMMON_H */ >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 6b93b04453..3ea18de06f 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -2226,6 +2226,16 @@ void riscv_cpu_list(void) >> g_slist_free(list); >> } >> +void riscv_cpu_list_props(CPUState *cs) >> +{ >> + char *enabled_isa; >> + >> + enabled_isa = riscv_isa_string(RISCV_CPU(cs)); >> + qemu_printf("Enable extension:\n"); > > I suggest "Enabled extensions". LGTM otherwise. Fixed, thanks. Zhiwei > > Daniel > >> + qemu_printf("\t%s\n", enabled_isa); >> + /* TODO: output all user configurable options and all possible >> extensions */ >> +} >> + >> #define DEFINE_CPU(type_name, initfn) \ >> { \ >> .name = type_name, \ >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> index 6ea22e0eea..af1d47605b 100644 >> --- a/target/riscv/cpu.h >> +++ b/target/riscv/cpu.h >> @@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr >> address, int size, >> bool probe, uintptr_t retaddr); >> char *riscv_isa_string(RISCVCPU *cpu); >> void riscv_cpu_list(void); >> +void riscv_cpu_list_props(CPUState *cs); >> void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); >> #define cpu_list riscv_cpu_list >> +#define cpu_list_props riscv_cpu_list_props >> #define cpu_mmu_index riscv_cpu_mmu_index >> #ifndef CONFIG_USER_ONLY
diff --git a/cpu.c b/cpu.c index e1a9239d0f..03a313cd72 100644 --- a/cpu.c +++ b/cpu.c @@ -299,6 +299,14 @@ void list_cpus(void) #endif } +void list_cpu_props(CPUState *cs) +{ + /* XXX: implement xxx_cpu_list_props for targets that still miss it */ +#if defined(cpu_list_props) + cpu_list_props(cs); +#endif +} + #if defined(CONFIG_USER_ONLY) void tb_invalidate_phys_addr(hwaddr addr) { diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 87dc9a752c..b3160d9218 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -166,5 +166,6 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, /* vl.c */ void list_cpus(void); +void list_cpu_props(CPUState *); #endif /* CPU_COMMON_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..3ea18de06f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2226,6 +2226,16 @@ void riscv_cpu_list(void) g_slist_free(list); } +void riscv_cpu_list_props(CPUState *cs) +{ + char *enabled_isa; + + enabled_isa = riscv_isa_string(RISCV_CPU(cs)); + qemu_printf("Enable extension:\n"); + qemu_printf("\t%s\n", enabled_isa); + /* TODO: output all user configurable options and all possible extensions */ +} + #define DEFINE_CPU(type_name, initfn) \ { \ .name = type_name, \ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..af1d47605b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -443,9 +443,11 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_list_props(CPUState *cs); void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); #define cpu_list riscv_cpu_list +#define cpu_list_props riscv_cpu_list_props #define cpu_mmu_index riscv_cpu_mmu_index #ifndef CONFIG_USER_ONLY
This API used for output current configuration for one specified CPU. Currently only RISC-V frontend implements this API. Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> --- cpu.c | 8 ++++++++ include/exec/cpu-common.h | 1 + target/riscv/cpu.c | 10 ++++++++++ target/riscv/cpu.h | 2 ++ 4 files changed, 21 insertions(+)