| Message ID | 20230804213355.294443-4-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg/ppc: Support power10 prefixed instructions | expand |
On Sat, Aug 5, 2023 at 7:33 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > When the offset is out of range of the non-prefixed insn, but > fits the 34-bit immediate of the prefixed insn, use that. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/ppc/tcg-target.c.inc | 66 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index 7fa2a2500b..d41c499b7d 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -323,6 +323,15 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) > #define STDX XO31(149) > #define STQ XO62( 2) > > +#define PLWA OPCD( 41) > +#define PLD OPCD( 57) > +#define PLXSD OPCD( 42) > +#define PLXV OPCD(25 * 2 + 1) /* force tx=1 */ > + > +#define PSTD OPCD( 61) > +#define PSTXSD OPCD( 46) > +#define PSTXV OPCD(27 * 2 + 1) /* force tx=1 */ PSTXV calls it sx not tx > + > #define ADDIC OPCD( 12) > #define ADDI OPCD( 14) > #define ADDIS OPCD( 15) > @@ -720,6 +729,20 @@ static void tcg_out_prefix_align(TCGContext *s) > } > } > > +/* Output Type 00 Prefix - 8-Byte Load/Store Form (8LS:D) */ > +static void tcg_out_8ls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, > + unsigned ra, tcg_target_long imm, bool r) > +{ > + tcg_insn_unit p, i; > + > + p = OPCD(1) | (r << 20) | ((imm >> 16) & 0x3ffff); > + i = opc | TAI(rt, ra, imm); > + > + tcg_out_prefix_align(s); > + tcg_out32(s, p); > + tcg_out32(s, i); > +} > + > /* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ > static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, > unsigned ra, tcg_target_long imm, bool r) > @@ -1364,6 +1387,49 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, > break; > } > > + /* For unaligned or large offsets, use the prefixed form. */ > + if (have_isa_3_10 > + && (offset != (int16_t)offset || (offset & align)) > + && offset == sextract64(offset, 0, 34)) { > + /* > + * Note that the MLS:D insns retain their un-prefixed opcode, > + * while the 8LS:D insns use a different opcode space. > + */ > + switch (opi) { > + case LBZ: > + case LHZ: > + case LHA: > + case LWZ: > + case STB: > + case STH: > + case STW: > + case ADDI: > + tcg_out_mls_d(s, opi, rt, base, offset, 0); > + return; > + case LWA: > + tcg_out_8ls_d(s, PLWA, rt, base, offset, 0); > + return; > + case LD: > + tcg_out_8ls_d(s, PLD, rt, base, offset, 0); > + return; > + case STD: > + tcg_out_8ls_d(s, PSTD, rt, base, offset, 0); > + return; > + case LXSD: > + tcg_out_8ls_d(s, PLXSD, rt & 31, base, offset, 0); > + return; > + case STXSD: > + tcg_out_8ls_d(s, PSTXSD, rt & 31, base, offset, 0); > + return; > + case LXV: > + tcg_out_8ls_d(s, PLXV, rt & 31, base, offset, 0); > + return; > + case STXV: > + tcg_out_8ls_d(s, PSTXV, rt & 31, base, offset, 0); > + return; > + } > + } > + > /* For unaligned, or very large offsets, use the indexed form. */ > if (offset & align || offset != (int32_t)offset || opi == 0) { > if (rs == base) { > -- > 2.34.1 > Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7fa2a2500b..d41c499b7d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -323,6 +323,15 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define STDX XO31(149) #define STQ XO62( 2) +#define PLWA OPCD( 41) +#define PLD OPCD( 57) +#define PLXSD OPCD( 42) +#define PLXV OPCD(25 * 2 + 1) /* force tx=1 */ + +#define PSTD OPCD( 61) +#define PSTXSD OPCD( 46) +#define PSTXV OPCD(27 * 2 + 1) /* force tx=1 */ + #define ADDIC OPCD( 12) #define ADDI OPCD( 14) #define ADDIS OPCD( 15) @@ -720,6 +729,20 @@ static void tcg_out_prefix_align(TCGContext *s) } } +/* Output Type 00 Prefix - 8-Byte Load/Store Form (8LS:D) */ +static void tcg_out_8ls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, + unsigned ra, tcg_target_long imm, bool r) +{ + tcg_insn_unit p, i; + + p = OPCD(1) | (r << 20) | ((imm >> 16) & 0x3ffff); + i = opc | TAI(rt, ra, imm); + + tcg_out_prefix_align(s); + tcg_out32(s, p); + tcg_out32(s, i); +} + /* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, unsigned ra, tcg_target_long imm, bool r) @@ -1364,6 +1387,49 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, break; } + /* For unaligned or large offsets, use the prefixed form. */ + if (have_isa_3_10 + && (offset != (int16_t)offset || (offset & align)) + && offset == sextract64(offset, 0, 34)) { + /* + * Note that the MLS:D insns retain their un-prefixed opcode, + * while the 8LS:D insns use a different opcode space. + */ + switch (opi) { + case LBZ: + case LHZ: + case LHA: + case LWZ: + case STB: + case STH: + case STW: + case ADDI: + tcg_out_mls_d(s, opi, rt, base, offset, 0); + return; + case LWA: + tcg_out_8ls_d(s, PLWA, rt, base, offset, 0); + return; + case LD: + tcg_out_8ls_d(s, PLD, rt, base, offset, 0); + return; + case STD: + tcg_out_8ls_d(s, PSTD, rt, base, offset, 0); + return; + case LXSD: + tcg_out_8ls_d(s, PLXSD, rt & 31, base, offset, 0); + return; + case STXSD: + tcg_out_8ls_d(s, PSTXSD, rt & 31, base, offset, 0); + return; + case LXV: + tcg_out_8ls_d(s, PLXV, rt & 31, base, offset, 0); + return; + case STXV: + tcg_out_8ls_d(s, PSTXV, rt & 31, base, offset, 0); + return; + } + } + /* For unaligned, or very large offsets, use the indexed form. */ if (offset & align || offset != (int32_t)offset || opi == 0) { if (rs == base) {
When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/ppc/tcg-target.c.inc | 66 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+)