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Fri, 04 Aug 2023 00:35:03 +0200 From: Helge Deller To: qemu-devel@nongnu.org, Peter Maydell , Richard Henderson Cc: Helge Deller , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org Subject: [PULL 1/1] target/hppa: Move iaoq registers and thus reduce generated code size Date: Fri, 4 Aug 2023 00:35:02 +0200 Message-ID: <20230803223502.653223-2-deller@gmx.de> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230803223502.653223-1-deller@gmx.de> References: <20230803223502.653223-1-deller@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:830NITqZd9ri1T3pjzcHAHxfBnquY0sXQSHQYQ9P8PHa52y6flJ ujb9MnFM8T436v0hXcAfQZ+5LW+ie84HbonWgQdIOw/eF5hSPt3/8p4ZMdqfc6ukGOgcFks qvWj02ozc/pAlOcj9YzeEh1VLgqmOqjyqrI9Xq4SdRAceYEyW1Ki9ZJcmPNU13vyE4EbNde DJghT3CbrIlJZzAh8cE3g== UI-OutboundReport: notjunk:1;M01:P0:wd/0gPt0QAM=;y/8uB2faRyRonPrhjLjIgM39EaS +axKW+dCCVPWUmIukCkH8N38tkw0dBfz3h0WLx7qvOGNV2kt4ub8AhjwrozCwP+C+Ko5oeiAn Jh4uXCKmwSRmFl/pJn9DDc5dQRg8yb8UkihQacKhk1GkfDmI+MaK9vmhJGh3zjG7z6+9aMmAX 5+I4nTSyYIdo054kYja+wwamGojH22QV/p2cEMu1iomqeCuw2pY7Ptb5UiUBjOkT1o7bLNLQ4 xOewD+BZoQ59JhHcAlSsf4Ej+W1Y1iAEJJbVnxSH8J2cdz05lJffAXBa6uevH95hk7Ipt0wlz ChBKaft863Acs27NIDWs881x5xV3ZNk8sbtxGIEbNp4Q1EfQXVZYj4k0lRAsXmP9zJSJ69rbB 4qpTHk3L6QONZKBsHPaG/JRwa5B02k70ObrjII1LkW8grhvrsZWw4GY+QGYSc8z7NiEDi/utP Jr8RAtPPyJztUQ05ySCGRsx1OQyyX+ddG9NXJxbNnaOLvvmftTcY8F/8ApGuF/phhxWmIFBft Oe8yKm90KjIF1gGgMs0PV+Ayix+CJSDpdCiMvYqHg8CNt3DhRGX+nDFy8NXTRG/1vEoclhvFO RYF+40q6fEozN6HIQBfD/EmjjifZ+KPAVpQoIpR2ZXyRTwkGjb2yksfoBEoGMkFSbTHmnwPYF YrZ2RZ4DsfrqrIVMjPXr0mcl12vNdXb5mQYXTY7ff+77qUgjOFYEQ0LN4/l/hydxJ7j7nL3NN sx7OUdnN9GhO8rsUJlUU6C182/I4alynwSML/ZAcnkUVdHYAcxuMVfb/+npuE1weUR9NSqO9h 11OnnKQMr0M7N+YCAwJHVCPqxgz5n4ZTziqNVc1WpuWjlLM/rx9lLxurY4oFPpkva2wSGLq7R EaFS33svvFMHSU5DH4KqFSKfFfWQuxvKzx1+/suWrUaYeDHCvie4w1xD21R29iPKU2KqxG7WO DEU5Jrm9eJ3clA9XUrNCen17788= Received-SPF: pass client-ip=212.227.15.19; envelope-from=deller@gmx.de; helo=mout.gmx.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On hppa the Instruction Address Offset Queue (IAOQ) registers specifies the next to-be-executed instructions addresses. Each generated TB writes those registers at least once, so those registers are used heavily in generated code. Looking at the generated assembly, for a x86-64 host this code to write the address $0x7ffe826f into iaoq_f is generated: 0x7f73e8000184: c7 85 d4 01 00 00 6f 82 movl $0x7ffe826f, 0x1d4(%rbp) 0x7f73e800018c: fe 7f 0x7f73e800018e: c7 85 d8 01 00 00 73 82 movl $0x7ffe8273, 0x1d8(%rbp) 0x7f73e8000196: fe 7f With the trivial change, by moving the variables iaoq_f and iaoq_b to the top of struct CPUArchState, the offset to %rbp is reduced (from 0x1d4 to 0), which allows the x86-64 tcg to generate 3 bytes less of generated code per move instruction: 0x7fc1e800018c: c7 45 00 6f 82 fe 7f movl $0x7ffe826f, (%rbp) 0x7fc1e8000193: c7 45 04 73 82 fe 7f movl $0x7ffe8273, 4(%rbp) Overall this is a reduction of generated code (not a reduction of number of instructions). A test run with checks the generated code size by running "/bin/ls" with qemu-user shows that the code size shrinks from 1616767 to 1569273 bytes, which is ~97% of the former size. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Helge Deller Cc: qemu-stable@nongnu.org --- target/hppa/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.41.0 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 9fe79b1242..75c5c0ccf7 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -168,6 +168,9 @@ typedef struct { } hppa_tlb_entry; typedef struct CPUArchState { + target_ureg iaoq_f; /* front */ + target_ureg iaoq_b; /* back, aka next instruction */ + target_ureg gr[32]; uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ @@ -186,8 +189,6 @@ typedef struct CPUArchState { target_ureg psw_cb; /* in least significant bit of next nibble */ target_ureg psw_cb_msb; /* boolean */ - target_ureg iaoq_f; /* front */ - target_ureg iaoq_b; /* back, aka next instruction */ uint64_t iasq_f; uint64_t iasq_b;