| Message ID | 20230720094223.27767-2-its@irrelevant.dk |
|---|---|
| State | New |
| Headers | show |
| Series | hw/nvme: use stl/ldl pci dma api | expand |
On 20/07/2023 11.42, Klaus Jensen wrote: > From: Klaus Jensen <k.jensen@samsung.com> > > Use the stl/ldl pci dma api for writing/reading doorbells. This removes > the explicit endian conversions. > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com> > --- > hw/nvme/ctrl.c | 42 +++++++++++++----------------------------- > 1 file changed, 13 insertions(+), 29 deletions(-) Reviewed-by: Thomas Huth <thuth@redhat.com>
On 20/7/23 11:42, Klaus Jensen wrote: > From: Klaus Jensen <k.jensen@samsung.com> > > Use the stl/ldl pci dma api for writing/reading doorbells. This removes > the explicit endian conversions. > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com> > --- > hw/nvme/ctrl.c | 42 +++++++++++++----------------------------- > 1 file changed, 13 insertions(+), 29 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On 7/20/23 11:42, Klaus Jensen wrote: > From: Klaus Jensen <k.jensen@samsung.com> > > Use the stl/ldl pci dma api for writing/reading doorbells. This removes > the explicit endian conversions. > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Tested-by: Cédric Le Goater <clg@redhat.com> on big and little endian hosts, Thanks, C. > --- > hw/nvme/ctrl.c | 42 +++++++++++++----------------------------- > 1 file changed, 13 insertions(+), 29 deletions(-) > > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > index dadc2dc7da10..f2e5a2fa737b 100644 > --- a/hw/nvme/ctrl.c > +++ b/hw/nvme/ctrl.c > @@ -1468,20 +1468,16 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, > > static void nvme_update_cq_eventidx(const NvmeCQueue *cq) > { > - uint32_t v = cpu_to_le32(cq->head); > - > trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head); > > - pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v)); > + stl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->ei_addr, cq->head, > + MEMTXATTRS_UNSPECIFIED); > } > > static void nvme_update_cq_head(NvmeCQueue *cq) > { > - uint32_t v; > - > - pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &v, sizeof(v)); > - > - cq->head = le32_to_cpu(v); > + ldl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head, > + MEMTXATTRS_UNSPECIFIED); > > trace_pci_nvme_update_cq_head(cq->cqid, cq->head); > } > @@ -6801,7 +6797,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) > PCIDevice *pci = PCI_DEVICE(n); > uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1); > uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2); > - uint32_t v; > int i; > > /* Address should be page aligned */ > @@ -6819,8 +6814,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) > NvmeCQueue *cq = n->cq[i]; > > if (sq) { > - v = cpu_to_le32(sq->tail); > - > /* > * CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3) > * nvme_process_db() uses this hard-coded way to calculate > @@ -6828,7 +6821,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) > */ > sq->db_addr = dbs_addr + (i << 3); > sq->ei_addr = eis_addr + (i << 3); > - pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail)); > + stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED); > > if (n->params.ioeventfd && sq->sqid != 0) { > if (!nvme_init_sq_ioeventfd(sq)) { > @@ -6838,12 +6831,10 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) > } > > if (cq) { > - v = cpu_to_le32(cq->head); > - > /* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */ > cq->db_addr = dbs_addr + (i << 3) + (1 << 2); > cq->ei_addr = eis_addr + (i << 3) + (1 << 2); > - pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head)); > + stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED); > > if (n->params.ioeventfd && cq->cqid != 0) { > if (!nvme_init_cq_ioeventfd(cq)) { > @@ -6974,20 +6965,16 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) > > static void nvme_update_sq_eventidx(const NvmeSQueue *sq) > { > - uint32_t v = cpu_to_le32(sq->tail); > - > trace_pci_nvme_update_sq_eventidx(sq->sqid, sq->tail); > > - pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &v, sizeof(v)); > + stl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->ei_addr, sq->tail, > + MEMTXATTRS_UNSPECIFIED); > } > > static void nvme_update_sq_tail(NvmeSQueue *sq) > { > - uint32_t v; > - > - pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &v, sizeof(v)); > - > - sq->tail = le32_to_cpu(v); > + ldl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail, > + MEMTXATTRS_UNSPECIFIED); > > trace_pci_nvme_update_sq_tail(sq->sqid, sq->tail); > } > @@ -7592,7 +7579,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) > static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > { > PCIDevice *pci = PCI_DEVICE(n); > - uint32_t qid, v; > + uint32_t qid; > > if (unlikely(addr & ((1 << 2) - 1))) { > NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, > @@ -7659,8 +7646,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > start_sqs = nvme_cq_full(cq) ? 1 : 0; > cq->head = new_head; > if (!qid && n->dbbuf_enabled) { > - v = cpu_to_le32(cq->head); > - pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head)); > + stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED); > } > if (start_sqs) { > NvmeSQueue *sq; > @@ -7720,8 +7706,6 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > > sq->tail = new_tail; > if (!qid && n->dbbuf_enabled) { > - v = cpu_to_le32(sq->tail); > - > /* > * The spec states "the host shall also update the controller's > * corresponding doorbell property to match the value of that entry > @@ -7735,7 +7719,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) > * including ones that run on Linux, are not updating Admin Queues, > * so we can't trust reading it for an appropriate sq tail. > */ > - pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail)); > + stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED); > } > > qemu_bh_schedule(sq->bh);
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index dadc2dc7da10..f2e5a2fa737b 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1468,20 +1468,16 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, static void nvme_update_cq_eventidx(const NvmeCQueue *cq) { - uint32_t v = cpu_to_le32(cq->head); - trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head); - pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v)); + stl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->ei_addr, cq->head, + MEMTXATTRS_UNSPECIFIED); } static void nvme_update_cq_head(NvmeCQueue *cq) { - uint32_t v; - - pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &v, sizeof(v)); - - cq->head = le32_to_cpu(v); + ldl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head, + MEMTXATTRS_UNSPECIFIED); trace_pci_nvme_update_cq_head(cq->cqid, cq->head); } @@ -6801,7 +6797,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) PCIDevice *pci = PCI_DEVICE(n); uint64_t dbs_addr = le64_to_cpu(req->cmd.dptr.prp1); uint64_t eis_addr = le64_to_cpu(req->cmd.dptr.prp2); - uint32_t v; int i; /* Address should be page aligned */ @@ -6819,8 +6814,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) NvmeCQueue *cq = n->cq[i]; if (sq) { - v = cpu_to_le32(sq->tail); - /* * CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3) * nvme_process_db() uses this hard-coded way to calculate @@ -6828,7 +6821,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) */ sq->db_addr = dbs_addr + (i << 3); sq->ei_addr = eis_addr + (i << 3); - pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail)); + stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED); if (n->params.ioeventfd && sq->sqid != 0) { if (!nvme_init_sq_ioeventfd(sq)) { @@ -6838,12 +6831,10 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) } if (cq) { - v = cpu_to_le32(cq->head); - /* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2) */ cq->db_addr = dbs_addr + (i << 3) + (1 << 2); cq->ei_addr = eis_addr + (i << 3) + (1 << 2); - pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head)); + stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED); if (n->params.ioeventfd && cq->cqid != 0) { if (!nvme_init_cq_ioeventfd(cq)) { @@ -6974,20 +6965,16 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequest *req) static void nvme_update_sq_eventidx(const NvmeSQueue *sq) { - uint32_t v = cpu_to_le32(sq->tail); - trace_pci_nvme_update_sq_eventidx(sq->sqid, sq->tail); - pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &v, sizeof(v)); + stl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->ei_addr, sq->tail, + MEMTXATTRS_UNSPECIFIED); } static void nvme_update_sq_tail(NvmeSQueue *sq) { - uint32_t v; - - pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &v, sizeof(v)); - - sq->tail = le32_to_cpu(v); + ldl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail, + MEMTXATTRS_UNSPECIFIED); trace_pci_nvme_update_sq_tail(sq->sqid, sq->tail); } @@ -7592,7 +7579,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size) static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) { PCIDevice *pci = PCI_DEVICE(n); - uint32_t qid, v; + uint32_t qid; if (unlikely(addr & ((1 << 2) - 1))) { NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, @@ -7659,8 +7646,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) start_sqs = nvme_cq_full(cq) ? 1 : 0; cq->head = new_head; if (!qid && n->dbbuf_enabled) { - v = cpu_to_le32(cq->head); - pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head)); + stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIFIED); } if (start_sqs) { NvmeSQueue *sq; @@ -7720,8 +7706,6 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) sq->tail = new_tail; if (!qid && n->dbbuf_enabled) { - v = cpu_to_le32(sq->tail); - /* * The spec states "the host shall also update the controller's * corresponding doorbell property to match the value of that entry @@ -7735,7 +7719,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) * including ones that run on Linux, are not updating Admin Queues, * so we can't trust reading it for an appropriate sq tail. */ - pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail)); + stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIFIED); } qemu_bh_schedule(sq->bh);