diff mbox series

[v2,1/5] ppc/pnv: quad xscom callbacks are P9 specific

Message ID 20230704054204.168547-2-joel@jms.id.au
State New
Headers show
Series ppc/pnv: Extend "quad" model for p10 | expand

Commit Message

Joel Stanley July 4, 2023, 5:42 a.m. UTC
Rename the functions to include P9 in the name in preparation for adding
P10 versions.

Correct the unimp read message while we're changing the function.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v2: Fix unimp print, and grammar in the commit message
---
 hw/ppc/pnv_core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

Comments

Frederic Barrat July 4, 2023, 9:59 a.m. UTC | #1
On 04/07/2023 07:42, Joel Stanley wrote:
> Rename the functions to include P9 in the name in preparation for adding
> P10 versions.
> 
> Correct the unimp read message while we're changing the function.
> 
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---


Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>


> v2: Fix unimp print, and grammar in the commit message
> ---
>   hw/ppc/pnv_core.c | 19 ++++++++++---------
>   1 file changed, 10 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 0bc3ad41c81c..0f451b3b6e1f 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -360,8 +360,8 @@ DEFINE_TYPES(pnv_core_infos)
>   
>   #define P9X_EX_NCU_SPEC_BAR                     0x11010
>   
> -static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
> -                                    unsigned int width)
> +static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
> +                                           unsigned int width)
>   {
>       uint32_t offset = addr >> 3;
>       uint64_t val = -1;
> @@ -372,15 +372,15 @@ static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
>           val = 0;
>           break;
>       default:
> -        qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
> +        qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
>                         offset);
>       }
>   
>       return val;
>   }
>   
> -static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> -                                 unsigned int width)
> +static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
> +                                        unsigned int width)
>   {
>       uint32_t offset = addr >> 3;
>   
> @@ -394,9 +394,9 @@ static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
>       }
>   }
>   
> -static const MemoryRegionOps pnv_quad_xscom_ops = {
> -    .read = pnv_quad_xscom_read,
> -    .write = pnv_quad_xscom_write,
> +static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> +    .read = pnv_quad_power9_xscom_read,
> +    .write = pnv_quad_power9_xscom_write,
>       .valid.min_access_size = 8,
>       .valid.max_access_size = 8,
>       .impl.min_access_size = 8,
> @@ -410,7 +410,8 @@ static void pnv_quad_realize(DeviceState *dev, Error **errp)
>       char name[32];
>   
>       snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
> -    pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
> +    pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
> +                          &pnv_quad_power9_xscom_ops,
>                             eq, name, PNV9_XSCOM_EQ_SIZE);
>   }
>
diff mbox series

Patch

diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 0bc3ad41c81c..0f451b3b6e1f 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -360,8 +360,8 @@  DEFINE_TYPES(pnv_core_infos)
 
 #define P9X_EX_NCU_SPEC_BAR                     0x11010
 
-static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
-                                    unsigned int width)
+static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr,
+                                           unsigned int width)
 {
     uint32_t offset = addr >> 3;
     uint64_t val = -1;
@@ -372,15 +372,15 @@  static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
         val = 0;
         break;
     default:
-        qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
+        qemu_log_mask(LOG_UNIMP, "%s: reading @0x%08x\n", __func__,
                       offset);
     }
 
     return val;
 }
 
-static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
-                                 unsigned int width)
+static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
+                                        unsigned int width)
 {
     uint32_t offset = addr >> 3;
 
@@ -394,9 +394,9 @@  static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
     }
 }
 
-static const MemoryRegionOps pnv_quad_xscom_ops = {
-    .read = pnv_quad_xscom_read,
-    .write = pnv_quad_xscom_write,
+static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
+    .read = pnv_quad_power9_xscom_read,
+    .write = pnv_quad_power9_xscom_write,
     .valid.min_access_size = 8,
     .valid.max_access_size = 8,
     .impl.min_access_size = 8,
@@ -410,7 +410,8 @@  static void pnv_quad_realize(DeviceState *dev, Error **errp)
     char name[32];
 
     snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
-    pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
+    pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
+                          &pnv_quad_power9_xscom_ops,
                           eq, name, PNV9_XSCOM_EQ_SIZE);
 }